From cf9136de4acc8de9c89f2d4dbeb377937bec51fc Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 28 Mar 2019 09:36:16 -0700 Subject: [PATCH 01/36] backport ucb-bar/project-template/pull/59 --- Makefrag | 2 +- barstools | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefrag b/Makefrag index 7cc4df34..85451645 100644 --- a/Makefrag +++ b/Makefrag @@ -35,7 +35,7 @@ SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf sim_dotf ?= $(build_dir)/sim_files.f -REPL_SEQ_MEM = --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) +REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) # This should match whatever the commonSettings version is in build.sbt BARSTOOLS_VER=1.0 diff --git a/barstools b/barstools index 9d505d60..0b9d74ad 160000 --- a/barstools +++ b/barstools @@ -1 +1 @@ -Subproject commit 9d505d6063f07f7750686f67d2cda49b17f6d898 +Subproject commit 0b9d74ada7e3271e82d665b09b3b9ff087c70f91 From 3425def36b5e202593e485013131ddfa59b01931 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 28 Mar 2019 11:47:32 -0700 Subject: [PATCH 02/36] Bumps barstools and fixes build system after (#63) Barstools now handles annotations correctly. This means that the blackboxresources for the harness and top are different and need to be merged in the build system. We also add all Sim*.cc files to default resources as our new emulator demands. We then remove them from the harness .f file to avoid having to detect which ones to include selectively. --- Makefrag | 6 +++++- barstools | 2 +- src/main/scala/example/Simulator.scala | 1 + verisim/Makefile | 7 ++----- vsim/Makefile | 4 +--- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Makefrag b/Makefrag index 85451645..88f07d6e 100644 --- a/Makefrag +++ b/Makefrag @@ -34,6 +34,8 @@ HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf sim_dotf ?= $(build_dir)/sim_files.f +sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f +sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) @@ -63,9 +65,11 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) $(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir) + cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) -$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) +$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(sim_top_blackboxes) $(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir) + grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs $(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR) diff --git a/barstools b/barstools index 0b9d74ad..8f7af5b0 160000 --- a/barstools +++ b/barstools @@ -1 +1 @@ -Subproject commit 0b9d74ada7e3271e82d665b09b3b9ff087c70f91 +Subproject commit 8f7af5b0bfe98597b68fe5414700c44036dcf899 diff --git a/src/main/scala/example/Simulator.scala b/src/main/scala/example/Simulator.scala index 0f142fd7..240f930f 100644 --- a/src/main/scala/example/Simulator.scala +++ b/src/main/scala/example/Simulator.scala @@ -82,6 +82,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { out.close() } def resources(sim: Simulator): Seq[String] = Seq( + "/testchipip/csrc/SimSerial.cc", "/csrc/SimDTM.cc", "/csrc/SimJTAG.cc", "/csrc/remote_bitbang.h", diff --git a/verisim/Makefile b/verisim/Makefile index dc3a219e..dbc5ee28 100644 --- a/verisim/Makefile +++ b/verisim/Makefile @@ -26,9 +26,6 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) -include $(build_dir)/$(long_name).d endif -sim_blackboxes = \ - $(build_dir)/firrtl_black_box_resource_files.f - rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc sim_vsrcs = \ @@ -49,7 +46,7 @@ $(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \ - -o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \ + -o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" touch $@ @@ -61,7 +58,7 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug $(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \ - -o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \ + -o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" touch $@ diff --git a/vsim/Makefile b/vsim/Makefile index bd8afc29..9baef0cf 100644 --- a/vsim/Makefile +++ b/vsim/Makefile @@ -22,8 +22,6 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) -include $(build_dir)/$(long_name).d endif -sim_blackboxes = \ - $(build_dir)/firrtl_black_box_resource_files.f rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc @@ -40,7 +38,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1 -CC "-I$(RISCV)/include" \ -CC "-std=c++11" \ -CC "-Wl,-rpath,$(RISCV)/lib" \ - -f $(sim_blackboxes) -f $(sim_dotf) \ + -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -f $(sim_dotf) \ $(RISCV)/lib/libfesvr.so \ -sverilog \ +incdir+$(generated_dir) \ From 5be8de1288e523ea2b5426093b0f5408f77abcd4 Mon Sep 17 00:00:00 2001 From: John Wright Date: Fri, 29 Mar 2019 14:00:52 -0700 Subject: [PATCH 03/36] Build additional annos and fir (#64) --- Makefrag | 17 +++++++++++------ barstools | 2 +- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/Makefrag b/Makefrag index 88f07d6e..8ac2260b 100644 --- a/Makefrag +++ b/Makefrag @@ -30,9 +30,14 @@ long_name=$(PROJECT).$(MODEL).$(CONFIG) FIRRTL_FILE ?=$(build_dir)/$(long_name).fir ANNO_FILE ?=$(build_dir)/$(long_name).anno.json VERILOG_FILE ?=$(build_dir)/$(long_name).top.v +TOP_FIR ?=$(build_dir)/$(long_name).top.fir +TOP_ANNO ?=$(build_dir)/$(long_name).top.anno.json HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v +HARNESS_FIR ?=$(build_dir)/$(long_name).harness.fir +HARNESS_ANNO ?=$(build_dir)/$(long_name).harness.anno.json SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf +SMEMS_FIR ?=$(build_dir)/$(long_name).mems.fir sim_dotf ?= $(build_dir)/sim_files.f sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f @@ -63,17 +68,17 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) mkdir -p $(build_dir) cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" -$(VERILOG_FILE) $(SMEMS_CONF): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) - $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) $(REPL_SEQ_MEM) -td $(build_dir) +$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) + $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir) cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) -$(HARNESS_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(sim_top_blackboxes) - $(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -td $(build_dir) +$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(sim_top_blackboxes) + $(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir) grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs -$(SMEMS_FILE): $(SMEMS_CONF) $(MACROCOMPILER_JAR) - $(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) --mode synflops +$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) $(MACROCOMPILER_JAR) + $(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) --mode synflops regression-tests = \ rv64ud-v-fcvt \ diff --git a/barstools b/barstools index 8f7af5b0..e548210e 160000 --- a/barstools +++ b/barstools @@ -1 +1 @@ -Subproject commit 8f7af5b0bfe98597b68fe5414700c44036dcf899 +Subproject commit e548210ef42e634e75cf283292685728114694c6 From 00d8e04d9382713fa70ab044d252c99570b84ae7 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 16 Apr 2019 21:15:00 -0700 Subject: [PATCH 04/36] Use SBT for barstools instead of jars (#66) * Use SBT for barstools instead of jars * Make MACROCOMPILER_MODE a variable This eases the downstream maintenance burden where `MACROCOMPILER_MODE` is not simply `--mode synflops` --- Makefrag | 34 +++++++--------------------------- 1 file changed, 7 insertions(+), 27 deletions(-) diff --git a/Makefrag b/Makefrag index 8ac2260b..3d36b3cb 100644 --- a/Makefrag +++ b/Makefrag @@ -44,23 +44,6 @@ sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) -# This should match whatever the commonSettings version is in build.sbt -BARSTOOLS_VER=1.0 -TAPEOUT_JAR=$(base_dir)/barstools/tapeout/target/scala-$(SCALA_VERSION_MAJOR)/tapeout-assembly-$(BARSTOOLS_VER).jar -MACROCOMPILER_JAR=$(base_dir)/barstools/macros/target/scala-$(SCALA_VERSION_MAJOR)/barstools-macros-assembly-$(BARSTOOLS_VER).jar - -TAPEOUT ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(TAPEOUT_JAR) -MACROCOMPILER ?= java -Xmx8G -Xss8M -cp $(ROCKET_CLASSES):$(TESTCHIPIP_CLASSES):$(MACROCOMPILER_JAR) - -$(TAPEOUT_JAR): $(call lookup_scala_srcs, $(base_dir)/barstools/tapeout/src/main/scala) - cd $(base_dir) && $(SBT) "tapeout/assembly" - -$(MACROCOMPILER_JAR): $(call lookup_scala_srcs, $(base_dir)/barstools/macros/src/main/scala) $(call lookup_scala_srcs, $(base_dir)/barstools/mdf/scalalib/src/main/scala) - cd $(base_dir) && $(SBT) "barstools-macros/assembly" - -.PHONY: jars -jars: $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) - $(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" @@ -68,17 +51,18 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) mkdir -p $(build_dir) cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" -$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) - $(TAPEOUT) barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir) +$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) -$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(TAPEOUT_JAR) $(sim_top_blackboxes) - $(TAPEOUT) barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir) +$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)" grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs -$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) $(MACROCOMPILER_JAR) - $(MACROCOMPILER) barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) --mode synflops +MACROCOMPILER_MODE ?= --mode synflops +$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) + cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)" regression-tests = \ rv64ud-v-fcvt \ @@ -113,7 +97,3 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% mkdir -p $(output_dir) ln -sf $< $@ -.PHONY: clean-scala -clean-scala: - rm -rf $(MACROCOMPILER_JAR) $(TAPEOUT_JAR) - From e007b49179b6edb36431a510f08b624f26f88ecd Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 14 May 2019 10:22:31 -0700 Subject: [PATCH 05/36] bump rocket-chip to enable large memory spaces (#76) * bump rocket-chip to enable large memory spaces * Tests pass with write mask bug fix * fix verisim build * Update to point to rocket-chip on master * bump rocket-chip and barstools This fixes the analog chisel bug and incorporates the firrtl MDF support (h/t John Wright) --- Makefrag | 16 ++++- barstools | 2 +- rocket-chip | 2 +- src/main/scala/example/Configs.scala | 15 ++++- src/main/scala/example/TestHarness.scala | 80 ++++++++++++++++++++++++ verisim/Makefile | 3 +- vsim/Makefile | 7 ++- 7 files changed, 116 insertions(+), 9 deletions(-) diff --git a/Makefrag b/Makefrag index 3d36b3cb..ab993500 100644 --- a/Makefrag +++ b/Makefrag @@ -8,7 +8,7 @@ SBT ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar $(ROCKETCHIP_DIR)/sbt-launch lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null) -PACKAGES=rocket-chip testchipip +PACKAGES=rocket-chip testchipip barstools SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*" @@ -25,7 +25,11 @@ build_dir=$(sim_dir)/generated-src CHISEL_ARGS ?= +ifneq ($(PROJECT),example) +long_name=$(PROJECT).$(CONFIG) +else long_name=$(PROJECT).$(MODEL).$(CONFIG) +endif FIRRTL_FILE ?=$(build_dir)/$(long_name).fir ANNO_FILE ?=$(build_dir)/$(long_name).anno.json @@ -35,6 +39,9 @@ TOP_ANNO ?=$(build_dir)/$(long_name).top.anno.json HARNESS_FILE ?=$(build_dir)/$(long_name).harness.v HARNESS_FIR ?=$(build_dir)/$(long_name).harness.fir HARNESS_ANNO ?=$(build_dir)/$(long_name).harness.anno.json +HARNESS_SMEMS_FILE ?=$(build_dir)/$(long_name).harness.mems.v +HARNESS_SMEMS_CONF ?=$(build_dir)/$(long_name).harness.mems.conf +HARNESS_SMEMS_FIR ?=$(build_dir)/$(long_name).harness.mems.fir SMEMS_FILE ?=$(build_dir)/$(long_name).mems.v SMEMS_CONF ?=$(build_dir)/$(long_name).mems.conf SMEMS_FIR ?=$(build_dir)/$(long_name).mems.fir @@ -43,6 +50,7 @@ sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) +HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF) $(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" @@ -56,7 +64,7 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)" + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)" grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs @@ -64,6 +72,10 @@ MACROCOMPILER_MODE ?= --mode synflops $(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)" +HARNESS_MACROCOMPILER_MODE = --mode synflops +$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) + cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" + regression-tests = \ rv64ud-v-fcvt \ rv64ud-p-fdiv \ diff --git a/barstools b/barstools index e548210e..7d3c3337 160000 --- a/barstools +++ b/barstools @@ -1 +1 @@ -Subproject commit e548210ef42e634e75cf283292685728114694c6 +Subproject commit 7d3c333765920ef9175c3d0eee6a6326f5e09a18 diff --git a/rocket-chip b/rocket-chip index a05728c4..b8baef6f 160000 --- a/rocket-chip +++ b/rocket-chip @@ -1 +1 @@ -Subproject commit a05728c4fab84a13585e14ac684b47c875b17b57 +Subproject commit b8baef6f26fa36c9b4e0b2a5eec12cd76ae5daf8 diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala index b7664614..3b009704 100644 --- a/src/main/scala/example/Configs.scala +++ b/src/main/scala/example/Configs.scala @@ -2,7 +2,7 @@ package example import chisel3._ import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.tile.XLen @@ -76,6 +76,19 @@ class WithFourTrackers extends WithNBlockDeviceTrackers(4) class WithTwoMemChannels extends WithNMemoryChannels(2) class WithFourMemChannels extends WithNMemoryChannels(4) +// 16GB of off chip memory +class BigMemoryConfig extends Config( + new WithExtMemSize((1<<30) * 16L) ++ new DefaultExampleConfig) +// 1GB of off chip memory +class GB1MemoryConfig extends Config( + new WithExtMemSize((1<<30) * 1L) ++ new DefaultExampleConfig) +class GB2MemoryConfig extends Config( + new WithExtMemSize((1<<30) * 2L) ++ new DefaultExampleConfig) +class GB4MemoryConfig extends Config( + new WithExtMemSize((1<<30) * 4L) ++ new DefaultExampleConfig) +class GB8MemoryConfig extends Config( + new WithExtMemSize((1<<30) * 8L) ++ new DefaultExampleConfig) + class DualCoreConfig extends Config( // Core gets tacked onto existing list new WithNBigCores(2) ++ new DefaultExampleConfig) diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala index a5af6240..2fcc42c4 100644 --- a/src/main/scala/example/TestHarness.scala +++ b/src/main/scala/example/TestHarness.scala @@ -6,6 +6,10 @@ import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp +import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} +import freechips.rocketchip.subsystem.RocketTilesKey +import freechips.rocketchip.tile.XLen +import scala.collection.mutable.LinkedHashSet case object BuildTop extends Field[(Clock, Bool, Parameters) => ExampleTopModule[ExampleTop]] @@ -36,6 +40,82 @@ class TestHarness(implicit val p: Parameters) extends Module { } object Generator extends GeneratorApp { + //Copied from rocketchip + val rv64RegrTestNames = LinkedHashSet( + "rv64ud-v-fcvt", + "rv64ud-p-fdiv", + "rv64ud-v-fadd", + "rv64uf-v-fadd", + "rv64um-v-mul", + "rv64mi-p-breakpoint", + "rv64uc-v-rvc", + "rv64ud-v-structural", + "rv64si-p-wfi", + "rv64um-v-divw", + "rv64ua-v-lrsc", + "rv64ui-v-fence_i", + "rv64ud-v-fcvt_w", + "rv64uf-v-fmin", + "rv64ui-v-sb", + "rv64ua-v-amomax_d", + "rv64ud-v-move", + "rv64ud-v-fclass", + "rv64ua-v-amoand_d", + "rv64ua-v-amoxor_d", + "rv64si-p-sbreak", + "rv64ud-v-fmadd", + "rv64uf-v-ldst", + "rv64um-v-mulh", + "rv64si-p-dirty") + + val rv32RegrTestNames = LinkedHashSet( + "rv32mi-p-ma_addr", + "rv32mi-p-csr", + "rv32ui-p-sh", + "rv32ui-p-lh", + "rv32uc-p-rvc", + "rv32mi-p-sbreak", + "rv32ui-p-sll") + + + override def addTestSuites { + import freechips.rocketchip.system.DefaultTestSuites._ + val xlen = params(XLen) + // TODO: for now only generate tests for the first core in the first subsystem + params(RocketTilesKey).headOption.map { tileParams => + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv32ud)) + } else { + TestGeneration.addSuite(rv32udBenchmarks) + TestGeneration.addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv64ud)) + } + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + } + //End copied from rocketchip val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs generateFirrtl generateAnno diff --git a/verisim/Makefile b/verisim/Makefile index dbc5ee28..f181f32b 100644 --- a/verisim/Makefile +++ b/verisim/Makefile @@ -31,6 +31,7 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc sim_vsrcs = \ $(VERILOG_FILE) \ $(HARNESS_FILE) \ + $(HARNESS_SMEMS_FILE) \ $(SMEMS_FILE) model_dir = $(build_dir)/$(long_name) @@ -82,5 +83,5 @@ run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regress run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests))) -clean: clean-scala +clean: rm -rf generated-src ./simulator-* diff --git a/vsim/Makefile b/vsim/Makefile index 9baef0cf..1e21e93f 100644 --- a/vsim/Makefile +++ b/vsim/Makefile @@ -28,6 +28,7 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc sim_vsrcs = \ $(VERILOG_FILE) \ $(HARNESS_FILE) \ + $(HARNESS_SMEMS_FILE) \ $(SMEMS_FILE) VCS = vcs -full64 @@ -62,13 +63,13 @@ $(simv_debug) : $(sim_vsrcs) $(sim_dotf) +define+DEBUG -debug_pp $(output_dir)/%.out: $(output_dir)/% $(simv) - $(simv) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + $(simv) +permissive -q +ntb_random_seed_automatic +verbose +max-cycles=1000000 +permissive-off $< 3>&1 1>&2 2>&3 | spike-dasm > $@ $(output_dir)/%.run: $(output_dir)/% $(simv) - $(simv) +max-cycles=1000000 $< && touch $@ + $(simv) +permissive -q +ntb_random_seed_automatic +max-cycles=1000000 +permissive-off $< && touch $@ $(output_dir)/%.vpd: $(output_dir)/% $(simv_debug) - $(simv_debug) +vcdplusfile=$@ +max-cycles=1000000 $< + $(simv_debug) +permissive -q +ntb_random_seed_automatic +vcdplusfile=$@ +max-cycles=1000000 +permissive-off $< run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests))) From e0e1acdd577ad2cabcfcabe9fb24e77e578e6cc9 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 15 May 2019 10:07:41 -0700 Subject: [PATCH 06/36] Bump barstools to master merged commit Fixes #86 --- barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/barstools b/barstools index 7d3c3337..82636b3f 160000 --- a/barstools +++ b/barstools @@ -1 +1 @@ -Subproject commit 7d3c333765920ef9175c3d0eee6a6326f5e09a18 +Subproject commit 82636b3ff43ecf6a0f0a7d46ebc2456b31e9703f From 8b3fef85cefdb98938e85e5cc01d7f529ba51b15 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 May 2019 17:44:47 -0700 Subject: [PATCH 07/36] first attempt at heter. port --- .../main/scala/BoomAndRocketSubsystem.scala | 94 ++++++++++++++ .../example/src/main/scala/ConfigMixins.scala | 66 ++++++++++ .../example/src/main/scala/Configs.scala | 120 +++++++++++++++++- .../scala/ExampleBoomAndRocketSystem.scala | 62 +++++++++ .../example/src/main/scala/TestHarness.scala | 35 +++++ generators/example/src/main/scala/Top.scala | 57 +++++++++ variables.mk | 12 ++ 7 files changed, 444 insertions(+), 2 deletions(-) create mode 100644 generators/example/src/main/scala/BoomAndRocketSubsystem.scala create mode 100644 generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala diff --git a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala new file mode 100644 index 00000000..275414ff --- /dev/null +++ b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala @@ -0,0 +1,94 @@ +package example + +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo} + +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.amba.axi4._ + +import boom.system.{BoomTilesKey} + +trait HasBoomAndRocketTiles extends HasTiles + with CanHavePeripheryPLIC + with CanHavePeripheryCLINT + with HasPeripheryDebug +{ this: BaseSubsystem => + + val module: HasBoomAndRocketTilesModuleImp + + protected val rocketTileParams = p(RocketTilesKey) + protected val boomTileParams = p(BoomTilesKey) + private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) + private val boomCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), boomTileParams.size) + + // Make a tile and wire its nodes into the system, + // according to the specified type of clock crossing. + // Note that we also inject new nodes into the tile itself, + // also based on the crossing type. + val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) => + val rocket = LazyModule(new RocketTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) + + connectMasterPortsToSBus(rocket, crossing) + connectSlavePortsToCBus(rocket, crossing) + connectInterrupts(rocket, Some(debug), clintOpt, plicOpt) + + rocket + } + + println(s"DEBUG: Amount of rocket tiles: ${rocketTiles.length}") + + val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) => + val boomCore = LazyModule( + new boom.common.BoomTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) + + connectMasterPortsToSBus(boomCore, crossing) + connectSlavePortsToCBus(boomCore, crossing) + connectInterrupts(boomCore, Some(debug), clintOpt, plicOpt) + + boomCore + } + + println(s"DEBUG: Amount of boom tiles: ${boomTiles.length}") + + val boomAndRocketTiles = rocketTiles ++ boomTiles + println(s"DEBUG: Amount of both tiles: ${boomAndRocketTiles.length}") + + def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++ + (boomTiles map { t => t.module.core.coreMonitorBundle}).toList + + def getOMRocketInterruptTargets(): Seq[OMInterruptTarget] = + boomAndRocketTiles.flatMap(c => c.cpuDevice.getInterruptTargets()) + + def getOMRocketCores(resourceBindingsMap: ResourceBindingsMap): Seq[OMComponent] = + boomAndRocketTiles.flatMap(c => c.cpuDevice.getOMComponents(resourceBindingsMap)) +} + +trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp + with HasPeripheryDebugModuleImp { + val outer: HasBoomAndRocketTiles +} + +class BoomAndRocketSubsystem(implicit p: Parameters) extends BaseSubsystem + with HasBoomAndRocketTiles { + val tiles = boomAndRocketTiles + override lazy val module = new BoomAndRocketSubsystemModuleImp(this) +} + +class BoomAndRocketSubsystemModuleImp[+L <: BoomAndRocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) + with HasBoomAndRocketTilesModuleImp { + tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => + wire.clock := clock + wire.reset := reset + wire.hartid := i.U + wire.reset_vector := global_reset_vector + } +} diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 5551a66d..02e4ea22 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -168,3 +168,69 @@ class WithGPIOBoomTop extends Config((site, here, up) => { top } }) + +// -------------------------------------- +// BOOM + Rocket Top Level System Parameter Mixins +// -------------------------------------- + +/** + * Class to specify a "plain" top level BOOM + Rocket system + */ +class WithNormalBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomAndRocketTop()(p)).module) + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with PWM + */ +class WithPWMBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomAndRocketTopWithPWMTL()(p)).module) +}) + +/** + * Class to specify a top level BOOM + Rocket system with a PWM AXI4 + */ +class WithPWMAXI4BoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomAndRocketTopWithPWMAXI4()(p)).module) +}) + +/** + * Class to specify a top level BOOM + Rocket system with a block device + */ +class WithBlockDeviceModelBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) + top.connectBlockDeviceModel() + top + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with a simulator block device + */ +class WithSimBlockDeviceBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) + top.connectSimBlockDevice(clock, reset) + top + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with GPIO + */ +class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithGPIO()(p)).module) + for (gpio <- top.gpio) { + for (pin <- gpio.pins) { + pin.i.ival := false.B + } + } + top + } +}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 68ca289c..97f08d62 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -106,10 +106,28 @@ class BlockDeviceModelBoomConfig extends Config( new WithBlockDeviceModelBoomTop ++ new BaseBoomConfig) +/** + * Slightly different looking configs since we need to override + * the `WithNBoomCores` with the DefaultBoomConfig params + */ class DualCoreBoomConfig extends Config( - // Core gets tacked onto existing list + new WithNormalBoomTop ++ + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(2) ++ - new DefaultBoomConfig) + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.system.BaseConfig) + +class DualCoreSmallBoomConfig extends Config( + new WithNormalBoomTop ++ + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.WithSmallBooms ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.system.BaseConfig) class RV32BoomConfig extends Config( new WithBootROM ++ @@ -119,3 +137,101 @@ class GPIOBoomConfig extends Config( new WithGPIO ++ new WithGPIOBoomTop ++ new BaseBoomConfig) + +// --------------------- +// BOOM + Rocket Configs +// --------------------- + +//class BaseRocketConfig extends Config( +// new WithBootROM ++ +// new freechips.rocketchip.system.DefaultConfig) +// +//class DefaultRocketConfig extends Config( +// new WithNormalRocketTop ++ +// new BaseRocketConfig) +// +//class BaseConfig extends Config( +// new WithDefaultMemPort() ++ +// new WithDefaultMMIOPort() ++ +// new WithDefaultSlavePort() ++ +// new WithTimebase(BigInt(1000000)) ++ // 1 MHz +// new WithDTS("freechips,rocketchip-unknown", Nil) ++ +// new WithNExtTopInterrupts(2) ++ +// new BaseSubsystemConfig() +//) +// +//class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig) +// +////boom +// new WithRVC ++ +// new DefaultBoomConfig ++ +// new WithNBoomCores(1) ++ +// new WithoutTLMonitors ++ +// new freechips.rocketchip.system.BaseConfig) + +class BaseBoomAndRocketConfig extends Config( + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +//class BaseBoomAndRocketConfig extends Config( +// new WithBootROM ++ +// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ +// new boom.system.BoomConfig) + +class SmallBaseBoomAndRocketConfig extends Config( + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new boom.system.SmallBoomConfig) + +class DefaultBoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class SmallDefaultBoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new SmallBaseBoomAndRocketConfig) + +class HwachaBoomAndRocketConfig extends Config( + new hwacha.DefaultHwachaConfig ++ + new DefaultBoomAndRocketConfig) + +class RoccBoomAndRocketConfig extends Config( + new WithRoccExample ++ + new DefaultBoomAndRocketConfig) + +class PWMBoomAndRocketConfig extends Config( + new WithPWMBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class PWMAXI4BoomAndRocketConfig extends Config( + new WithPWMAXI4BoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class SimBlockDeviceBoomAndRocketConfig extends Config( + new WithBlockDevice ++ + new WithSimBlockDeviceBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class BlockDeviceModelBoomAndRocketConfig extends Config( + new WithBlockDevice ++ + new WithBlockDeviceModelBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class DualCoreBoomAndOneRocketConfig extends Config( + // Core gets tacked onto existing list + new boom.system.WithNBoomCores(2) ++ + new DefaultBoomAndRocketConfig) + +class RV32BoomAndNormalRocketConfig extends Config( + new WithBootROM ++ + new boom.system.SmallRV32UnifiedBoomConfig) + +class GPIOBoomAndRocketConfig extends Config( + new WithGPIO ++ + new WithGPIOBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) diff --git a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala new file mode 100644 index 00000000..cc7fd3db --- /dev/null +++ b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala @@ -0,0 +1,62 @@ +package example + +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo} + +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.amba.axi4._ + +import boom.system.{BoomTilesKey} + +/** + * Example top with periphery devices and ports, and a BOOM subsystem + */ +class ExampleBoomAndRocketSystem(implicit p: Parameters) extends BoomAndRocketSubsystem + with HasAsyncExtInterrupts + with boom.system.CanHaveMisalignedMasterAXI4MemPort + with CanHaveMasterAXI4MMIOPort + with CanHaveSlaveAXI4Port + with HasPeripheryBootROM +{ + override lazy val module = new ExampleBoomAndRocketSystemModule(this) + + // The sbus masters the cbus; here we convert TL-UH -> TL-UL + sbus.crossToBus(cbus, NoCrossing) + + // The cbus masters the pbus; which might be clocked slower + cbus.crossToBus(pbus, SynchronousCrossing()) + + // The fbus masters the sbus; both are TL-UH or TL-C + FlipRendering { implicit p => + sbus.crossFromBus(fbus, SynchronousCrossing()) + } + + // The sbus masters the mbus; here we convert TL-C -> TL-UH + private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) + private val (in, out, halt) = coherenceManager(this) + if (nBanks != 0) { + sbus.coupleTo("coherence_manager") { in :*= _ } + mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } + } +} + +/** + * Example top module with periphery devices and ports, and a BOOM subsystem + */ +class ExampleBoomAndRocketSystemModule[+L <: ExampleBoomAndRocketSystem](_outer: L) extends BoomAndRocketSubsystemModuleImp(_outer) + with HasRTCModuleImp + with HasExtInterruptsModuleImp + with boom.system.CanHaveMisalignedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MMIOPortModuleImp + with CanHaveSlaveAXI4PortModuleImp + with HasPeripheryBootROMModuleImp + with DontTouch diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index b7120329..a517b6b8 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -77,3 +77,38 @@ class BoomTestHarness(implicit val p: Parameters) extends Module { }) io.success := dut.connectSimSerial() } + +// -------------------------- +// BOOM + Rocket Test Harness +// -------------------------- + +case object BuildBoomAndRocketTop extends Field[(Clock, Bool, Parameters) => BoomAndRocketTopModule[BoomAndRocketTop]] + +class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + // force Chisel to rename module + override def desiredName = "TestHarness" + + val dut = p(BuildBoomAndRocketTop)(clock, reset.toBool, p) + dut.debug := DontCare + dut.connectSimAXIMem() + dut.connectSimAXIMMIO() + dut.dontTouchPorts() + dut.tieOffInterrupts() + dut.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case core.ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case core.ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + io.success := dut.connectSimSerial() +} diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 8a39e3d1..50e5d0c6 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -127,3 +127,60 @@ class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop class BoomTopWithGPIOModule(l: BoomTopWithGPIO) extends BoomTopModule(l) with HasPeripheryGPIOModuleImp + +// ------------------------------- +// BOOM + Rocket Top Level Systems +// ------------------------------- + +class BoomAndRocketTop(implicit p: Parameters) extends ExampleBoomAndRocketSystem + with HasNoDebug + with HasPeripherySerial { + override lazy val module = new BoomAndRocketTopModule(this) +} + +class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends ExampleBoomAndRocketSystemModule(l) + with HasRTCModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with DontTouch + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithPWMTL(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryPWMTL { + override lazy val module = new BoomAndRocketTopWithPWMTLModule(this) +} + +class BoomAndRocketTopWithPWMTLModule(l: BoomAndRocketTopWithPWMTL) extends BoomAndRocketTopModule(l) + with HasPeripheryPWMTLModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryPWMAXI4 { + override lazy val module = new BoomAndRocketTopWithPWMAXI4Module(this) +} + +class BoomAndRocketTopWithPWMAXI4Module(l: BoomAndRocketTopWithPWMAXI4) extends BoomAndRocketTopModule(l) + with HasPeripheryPWMAXI4ModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithBlockDevice(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryBlockDevice { + override lazy val module = new BoomAndRocketTopWithBlockDeviceModule(this) +} + +class BoomAndRocketTopWithBlockDeviceModule(l: BoomAndRocketTopWithBlockDevice) extends BoomAndRocketTopModule(l) + with HasPeripheryBlockDeviceModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithGPIO(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryGPIO { + override lazy val module = new BoomAndRocketTopWithGPIOModule(this) +} + +class BoomAndRocketTopWithGPIOModule(l: BoomAndRocketTopWithGPIO) + extends BoomAndRocketTopModule(l) + with HasPeripheryGPIOModuleImp diff --git a/variables.mk b/variables.mk index 0808003c..62cd35ce 100644 --- a/variables.mk +++ b/variables.mk @@ -50,6 +50,18 @@ ifeq ($(SUB_PROJECT),boomexample) TB ?= TestDriver TOP ?= BoomTop endif +# for a BOOM + Rocket based example system +ifeq ($(SUB_PROJECT),boomrocketexample) + SBT_PROJECT ?= example + MODEL ?= BoomAndRocketTestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= $(SBT_PROJECT) + CONFIG ?= DefaultBoomAndRocketConfig + CONFIG_PACKAGE ?= $(SBT_PROJECT) + GENERATOR_PACKAGE ?= $(SBT_PROJECT) + TB ?= TestDriver + TOP ?= BoomAndRocketTop +endif # for BOOM developers ifeq ($(SUB_PROJECT),boom) SBT_PROJECT ?= boom From cae63ad13fffce885fe704e8f26861920be392cd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 May 2019 23:29:48 -0700 Subject: [PATCH 08/36] working heterogenous cores --- .../example/src/main/scala/ConfigMixins.scala | 26 ++++- .../example/src/main/scala/Configs.scala | 99 +++++++++---------- 2 files changed, 70 insertions(+), 55 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 02e4ea22..2816352d 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -1,14 +1,20 @@ package example import chisel3._ +import chisel3.util.{log2Up} + import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.{XLen} +import freechips.rocketchip.tile.{XLen, MaxHartIdBits} + import testchipip._ + import sifive.blocks.devices.gpio._ +import boom.system.{BoomTilesKey} + /** * TODO: Why do we need this? */ @@ -234,3 +240,19 @@ class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { top } }) + +/** + * Class to renumber BOOM + Rocket harts so that there are no overlapped harts + * This mixin assumes Rocket tiles are numbered before BOOM tiles + * Also makes support for multiple harts depend on Rocket + BOOM + * Note: Must come after all harts are assigned for it to apply + */ +class WithRenumberHarts extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => + r.copy(hartId = i) + } + case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => + b.copy(hartId = i + up(RocketTilesKey, site).length) + } + case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) +}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 97f08d62..74e9a131 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -1,8 +1,10 @@ package example import chisel3._ + import freechips.rocketchip.config.{Config} import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks} + import testchipip._ // -------------- @@ -43,6 +45,11 @@ class BlockDeviceModelRocketConfig extends Config( new WithBlockDeviceModelRocketTop ++ new BaseRocketConfig) +class GPIORocketConfig extends Config( + new WithGPIO ++ + new WithGPIORocketTop ++ + new BaseRocketConfig) + class DualCoreRocketConfig extends Config( new WithNBigCores(2) ++ new DefaultRocketConfig) @@ -51,11 +58,6 @@ class RV32RocketConfig extends Config( new WithRV32 ++ new DefaultRocketConfig) -class GPIORocketConfig extends Config( - new WithGPIO ++ - new WithGPIORocketTop ++ - new BaseRocketConfig) - class GB1MemoryConfig extends Config( new WithExtMemSize((1<<30) * 1L) ++ new DefaultRocketConfig) @@ -106,6 +108,11 @@ class BlockDeviceModelBoomConfig extends Config( new WithBlockDeviceModelBoomTop ++ new BaseBoomConfig) +class GPIOBoomConfig extends Config( + new WithGPIO ++ + new WithGPIOBoomTop ++ + new BaseBoomConfig) + /** * Slightly different looking configs since we need to override * the `WithNBoomCores` with the DefaultBoomConfig params @@ -129,48 +136,18 @@ class DualCoreSmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.system.BaseConfig) -class RV32BoomConfig extends Config( +class RV32UnifiedBoomConfig extends Config( + new WithNormalBoomTop ++ new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) -class GPIOBoomConfig extends Config( - new WithGPIO ++ - new WithGPIOBoomTop ++ - new BaseBoomConfig) - // --------------------- // BOOM + Rocket Configs // --------------------- -//class BaseRocketConfig extends Config( -// new WithBootROM ++ -// new freechips.rocketchip.system.DefaultConfig) -// -//class DefaultRocketConfig extends Config( -// new WithNormalRocketTop ++ -// new BaseRocketConfig) -// -//class BaseConfig extends Config( -// new WithDefaultMemPort() ++ -// new WithDefaultMMIOPort() ++ -// new WithDefaultSlavePort() ++ -// new WithTimebase(BigInt(1000000)) ++ // 1 MHz -// new WithDTS("freechips,rocketchip-unknown", Nil) ++ -// new WithNExtTopInterrupts(2) ++ -// new BaseSubsystemConfig() -//) -// -//class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig) -// -////boom -// new WithRVC ++ -// new DefaultBoomConfig ++ -// new WithNBoomCores(1) ++ -// new WithoutTLMonitors ++ -// new freechips.rocketchip.system.BaseConfig) - class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ + new WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(1) ++ @@ -178,15 +155,16 @@ class BaseBoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) -//class BaseBoomAndRocketConfig extends Config( -// new WithBootROM ++ -// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ -// new boom.system.BoomConfig) - class SmallBaseBoomAndRocketConfig extends Config( new WithBootROM ++ + new WithRenumberHarts ++ + new boom.common.WithRVC ++ + new boom.common.WithSmallBooms ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new boom.system.SmallBoomConfig) + new freechips.rocketchip.system.BaseConfig) class DefaultBoomAndRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ @@ -222,16 +200,31 @@ class BlockDeviceModelBoomAndRocketConfig extends Config( new WithBlockDeviceModelBoomAndRocketTop ++ new BaseBoomAndRocketConfig) -class DualCoreBoomAndOneRocketConfig extends Config( - // Core gets tacked onto existing list - new boom.system.WithNBoomCores(2) ++ - new DefaultBoomAndRocketConfig) - -class RV32BoomAndNormalRocketConfig extends Config( - new WithBootROM ++ - new boom.system.SmallRV32UnifiedBoomConfig) - class GPIOBoomAndRocketConfig extends Config( new WithGPIO ++ new WithGPIOBoomAndRocketTop ++ new BaseBoomAndRocketConfig) + +class DualCoreBoomAndOneRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new WithBootROM ++ + new WithRenumberHarts ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class RV32BoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new WithBootROM ++ + new WithRenumberHarts ++ + new boom.common.WithBoomRV32 ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new WithRV32 ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) From e538e333a5be1af1903d89932554234b61302c88 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 21 May 2019 10:47:24 -0700 Subject: [PATCH 09/36] updated boom for fixes \ better printf From 838a34be51e57832b72d13b9b35172f068236437 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 19:26:08 -0700 Subject: [PATCH 10/36] move subsystem to boom | misc cleanup | bump boom --- generators/boom | 2 +- .../main/scala/BoomAndRocketSubsystem.scala | 94 ------------------- .../example/src/main/scala/ConfigMixins.scala | 82 ---------------- .../example/src/main/scala/Configs.scala | 28 +++--- .../scala/ExampleBoomAndRocketSystem.scala | 62 ------------ .../example/src/main/scala/TestHarness.scala | 35 ------- generators/example/src/main/scala/Top.scala | 61 +----------- variables.mk | 5 +- 8 files changed, 19 insertions(+), 350 deletions(-) delete mode 100644 generators/example/src/main/scala/BoomAndRocketSubsystem.scala delete mode 100644 generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala diff --git a/generators/boom b/generators/boom index 8d3162cb..ff8c25af 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 8d3162cbbe6f0db19a39a2f22226ab9eb6edea31 +Subproject commit ff8c25af0b14c7eba67451f574e1ddacaaf8a5b6 diff --git a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala deleted file mode 100644 index 275414ff..00000000 --- a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala +++ /dev/null @@ -1,94 +0,0 @@ -package example - -import chisel3._ -import chisel3.internal.sourceinfo.{SourceInfo} - -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.axi4._ - -import boom.system.{BoomTilesKey} - -trait HasBoomAndRocketTiles extends HasTiles - with CanHavePeripheryPLIC - with CanHavePeripheryCLINT - with HasPeripheryDebug -{ this: BaseSubsystem => - - val module: HasBoomAndRocketTilesModuleImp - - protected val rocketTileParams = p(RocketTilesKey) - protected val boomTileParams = p(BoomTilesKey) - private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) - private val boomCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), boomTileParams.size) - - // Make a tile and wire its nodes into the system, - // according to the specified type of clock crossing. - // Note that we also inject new nodes into the tile itself, - // also based on the crossing type. - val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) => - val rocket = LazyModule(new RocketTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) - - connectMasterPortsToSBus(rocket, crossing) - connectSlavePortsToCBus(rocket, crossing) - connectInterrupts(rocket, Some(debug), clintOpt, plicOpt) - - rocket - } - - println(s"DEBUG: Amount of rocket tiles: ${rocketTiles.length}") - - val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) => - val boomCore = LazyModule( - new boom.common.BoomTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) - - connectMasterPortsToSBus(boomCore, crossing) - connectSlavePortsToCBus(boomCore, crossing) - connectInterrupts(boomCore, Some(debug), clintOpt, plicOpt) - - boomCore - } - - println(s"DEBUG: Amount of boom tiles: ${boomTiles.length}") - - val boomAndRocketTiles = rocketTiles ++ boomTiles - println(s"DEBUG: Amount of both tiles: ${boomAndRocketTiles.length}") - - def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++ - (boomTiles map { t => t.module.core.coreMonitorBundle}).toList - - def getOMRocketInterruptTargets(): Seq[OMInterruptTarget] = - boomAndRocketTiles.flatMap(c => c.cpuDevice.getInterruptTargets()) - - def getOMRocketCores(resourceBindingsMap: ResourceBindingsMap): Seq[OMComponent] = - boomAndRocketTiles.flatMap(c => c.cpuDevice.getOMComponents(resourceBindingsMap)) -} - -trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp - with HasPeripheryDebugModuleImp { - val outer: HasBoomAndRocketTiles -} - -class BoomAndRocketSubsystem(implicit p: Parameters) extends BaseSubsystem - with HasBoomAndRocketTiles { - val tiles = boomAndRocketTiles - override lazy val module = new BoomAndRocketSubsystemModuleImp(this) -} - -class BoomAndRocketSubsystemModuleImp[+L <: BoomAndRocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) - with HasBoomAndRocketTilesModuleImp { - tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => - wire.clock := clock - wire.reset := reset - wire.hartid := i.U - wire.reset_vector := global_reset_vector - } -} diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 2816352d..363f0895 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -109,72 +109,6 @@ class WithGPIORocketTop extends Config((site, here, up) => { } }) -// -------------------------------------- -// BOOM Top Level System Parameter Mixins -// -------------------------------------- - -/** - * Class to specify a "plain" top level BOOM system - */ -class WithNormalBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomTop()(p)).module) - } -}) - -/** - * Class to specify a top level BOOM system with PWM - */ -class WithPWMBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomTopWithPWMTL()(p)).module) -}) - -/** - * Class to specify a top level BOOM system with a PWM AXI4 - */ -class WithPWMAXI4BoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomTopWithPWMAXI4()(p)).module) -}) - -/** - * Class to specify a top level BOOM system with a block device - */ -class WithBlockDeviceModelBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) - top.connectBlockDeviceModel() - top - } -}) - -/** - * Class to specify a top level BOOM system with a simulator block device - */ -class WithSimBlockDeviceBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithBlockDevice()(p)).module) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -/** - * Class to specify a top level BOOM system with GPIO - */ -class WithGPIOBoomTop extends Config((site, here, up) => { - case BuildBoomTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomTopWithGPIO()(p)).module) - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } -}) - // -------------------------------------- // BOOM + Rocket Top Level System Parameter Mixins // -------------------------------------- @@ -240,19 +174,3 @@ class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { top } }) - -/** - * Class to renumber BOOM + Rocket harts so that there are no overlapped harts - * This mixin assumes Rocket tiles are numbered before BOOM tiles - * Also makes support for multiple harts depend on Rocket + BOOM - * Note: Must come after all harts are assigned for it to apply - */ -class WithRenumberHarts extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => - r.copy(hartId = i) - } - case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => - b.copy(hartId = i + up(RocketTilesKey, site).length) - } - case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) -}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 74e9a131..ee17916f 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -75,11 +75,11 @@ class SmallBaseBoomConfig extends Config( new boom.system.SmallBoomConfig) class DefaultBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new BaseBoomConfig) class SmallDefaultBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new SmallBaseBoomConfig) class HwachaBoomConfig extends Config( @@ -91,26 +91,26 @@ class RoccBoomConfig extends Config( new DefaultBoomConfig) class PWMBoomConfig extends Config( - new WithPWMBoomTop ++ + new WithPWMBoomAndRocketTop ++ new BaseBoomConfig) class PWMAXI4BoomConfig extends Config( - new WithPWMAXI4BoomTop ++ + new WithPWMAXI4BoomAndRocketTop ++ new BaseBoomConfig) class SimBlockDeviceBoomConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomTop ++ + new WithSimBlockDeviceBoomAndRocketTop ++ new BaseBoomConfig) class BlockDeviceModelBoomConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomTop ++ + new WithBlockDeviceModelBoomAndRocketTop ++ new BaseBoomConfig) class GPIOBoomConfig extends Config( new WithGPIO ++ - new WithGPIOBoomTop ++ + new WithGPIOBoomAndRocketTop ++ new BaseBoomConfig) /** @@ -118,7 +118,7 @@ class GPIOBoomConfig extends Config( * the `WithNBoomCores` with the DefaultBoomConfig params */ class DualCoreBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ @@ -127,7 +127,7 @@ class DualCoreBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreSmallBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ @@ -137,7 +137,7 @@ class DualCoreSmallBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class RV32UnifiedBoomConfig extends Config( - new WithNormalBoomTop ++ + new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) @@ -147,7 +147,7 @@ class RV32UnifiedBoomConfig extends Config( class BaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(1) ++ @@ -157,7 +157,7 @@ class BaseBoomAndRocketConfig extends Config( class SmallBaseBoomAndRocketConfig extends Config( new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ new boom.common.DefaultBoomConfig ++ @@ -208,7 +208,7 @@ class GPIOBoomAndRocketConfig extends Config( class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(2) ++ @@ -219,7 +219,7 @@ class DualCoreBoomAndOneRocketConfig extends Config( class RV32BoomAndRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ new WithBootROM ++ - new WithRenumberHarts ++ + new boom.system.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ diff --git a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala deleted file mode 100644 index cc7fd3db..00000000 --- a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala +++ /dev/null @@ -1,62 +0,0 @@ -package example - -import chisel3._ -import chisel3.internal.sourceinfo.{SourceInfo} - -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} -import freechips.rocketchip.tile._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.interrupts._ -import freechips.rocketchip.util._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.axi4._ - -import boom.system.{BoomTilesKey} - -/** - * Example top with periphery devices and ports, and a BOOM subsystem - */ -class ExampleBoomAndRocketSystem(implicit p: Parameters) extends BoomAndRocketSubsystem - with HasAsyncExtInterrupts - with boom.system.CanHaveMisalignedMasterAXI4MemPort - with CanHaveMasterAXI4MMIOPort - with CanHaveSlaveAXI4Port - with HasPeripheryBootROM -{ - override lazy val module = new ExampleBoomAndRocketSystemModule(this) - - // The sbus masters the cbus; here we convert TL-UH -> TL-UL - sbus.crossToBus(cbus, NoCrossing) - - // The cbus masters the pbus; which might be clocked slower - cbus.crossToBus(pbus, SynchronousCrossing()) - - // The fbus masters the sbus; both are TL-UH or TL-C - FlipRendering { implicit p => - sbus.crossFromBus(fbus, SynchronousCrossing()) - } - - // The sbus masters the mbus; here we convert TL-C -> TL-UH - private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) - private val (in, out, halt) = coherenceManager(this) - if (nBanks != 0) { - sbus.coupleTo("coherence_manager") { in :*= _ } - mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } - } -} - -/** - * Example top module with periphery devices and ports, and a BOOM subsystem - */ -class ExampleBoomAndRocketSystemModule[+L <: ExampleBoomAndRocketSystem](_outer: L) extends BoomAndRocketSubsystemModuleImp(_outer) - with HasRTCModuleImp - with HasExtInterruptsModuleImp - with boom.system.CanHaveMisalignedMasterAXI4MemPortModuleImp - with CanHaveMasterAXI4MMIOPortModuleImp - with CanHaveSlaveAXI4PortModuleImp - with HasPeripheryBootROMModuleImp - with DontTouch diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index a517b6b8..3d488c1c 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -43,41 +43,6 @@ class RocketTestHarness(implicit val p: Parameters) extends Module { io.success := dut.connectSimSerial() } -// ----------------- -// BOOM Test Harness -// ----------------- - -case object BuildBoomTop extends Field[(Clock, Bool, Parameters) => BoomTopModule[BoomTop]] - -class BoomTestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - // force Chisel to rename module - override def desiredName = "TestHarness" - - val dut = p(BuildBoomTop)(clock, reset.toBool, p) - dut.debug := DontCare - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - io.success := dut.connectSimSerial() -} - // -------------------------- // BOOM + Rocket Test Harness // -------------------------- diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 50e5d0c6..a481deef 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -71,74 +71,17 @@ class RocketTopWithGPIOModule(l: RocketTopWithGPIO) extends RocketTopModule(l) with HasPeripheryGPIOModuleImp -// ---------------------- -// BOOM Top Level Systems -// ---------------------- - -class BoomTop(implicit p: Parameters) extends boom.system.ExampleBoomSystem - with HasNoDebug - with HasPeripherySerial { - override lazy val module = new BoomTopModule(this) -} - -class BoomTopModule[+L <: BoomTop](l: L) extends boom.system.ExampleBoomSystemModule(l) - with HasRTCModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp - with DontTouch - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithPWMTL(implicit p: Parameters) extends BoomTop - with HasPeripheryPWMTL { - override lazy val module = new BoomTopWithPWMTLModule(this) -} - -class BoomTopWithPWMTLModule(l: BoomTopWithPWMTL) extends BoomTopModule(l) - with HasPeripheryPWMTLModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithPWMAXI4(implicit p: Parameters) extends BoomTop - with HasPeripheryPWMAXI4 { - override lazy val module = new BoomTopWithPWMAXI4Module(this) -} - -class BoomTopWithPWMAXI4Module(l: BoomTopWithPWMAXI4) extends BoomTopModule(l) - with HasPeripheryPWMAXI4ModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithBlockDevice(implicit p: Parameters) extends BoomTop - with HasPeripheryBlockDevice { - override lazy val module = new BoomTopWithBlockDeviceModule(this) -} - -class BoomTopWithBlockDeviceModule(l: BoomTopWithBlockDevice) extends BoomTopModule(l) - with HasPeripheryBlockDeviceModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop - with HasPeripheryGPIO { - override lazy val module = new BoomTopWithGPIOModule(this) -} - -class BoomTopWithGPIOModule(l: BoomTopWithGPIO) - extends BoomTopModule(l) - with HasPeripheryGPIOModuleImp - // ------------------------------- // BOOM + Rocket Top Level Systems // ------------------------------- -class BoomAndRocketTop(implicit p: Parameters) extends ExampleBoomAndRocketSystem +class BoomAndRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem with HasNoDebug with HasPeripherySerial { override lazy val module = new BoomAndRocketTopModule(this) } -class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends ExampleBoomAndRocketSystemModule(l) +class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) with HasRTCModuleImp with HasNoDebugModuleImp with HasPeripherySerialModuleImp diff --git a/variables.mk b/variables.mk index 62cd35ce..fb4f3632 100644 --- a/variables.mk +++ b/variables.mk @@ -48,7 +48,7 @@ ifeq ($(SUB_PROJECT),boomexample) CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= BoomTop + TOP ?= BoomAndRocketTop endif # for a BOOM + Rocket based example system ifeq ($(SUB_PROJECT),boomrocketexample) @@ -72,7 +72,7 @@ ifeq ($(SUB_PROJECT),boom) CONFIG_PACKAGE ?= boom.system GENERATOR_PACKAGE ?= boom.system TB ?= TestDriver - TOP ?= ExampleBoomSystem + TOP ?= ExampleBoomAndRocketSystem endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) @@ -186,4 +186,3 @@ sim_vsrcs = \ # assembly/benchmark variables ######################################################################################### timeout_cycles = 10000000 -bmark_timeout_cycles = 100000000 From 9182c1394abd19858534413915052819eadb0c34 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 21:46:37 -0700 Subject: [PATCH 11/36] update boom | fix comments and remove extra code --- generators/boom | 2 +- generators/example/src/main/scala/ConfigMixins.scala | 4 ++-- generators/example/src/main/scala/Top.scala | 1 - 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/generators/boom b/generators/boom index ff8c25af..734d62c6 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit ff8c25af0b14c7eba67451f574e1ddacaaf8a5b6 +Subproject commit 734d62c6a91920f62730a4a076f8dfce29c52bf2 diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 363f0895..1380b90b 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -109,9 +109,9 @@ class WithGPIORocketTop extends Config((site, here, up) => { } }) -// -------------------------------------- +// ----------------------------------------------- // BOOM + Rocket Top Level System Parameter Mixins -// -------------------------------------- +// ----------------------------------------------- /** * Class to specify a "plain" top level BOOM + Rocket system diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index a481deef..59493492 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -82,7 +82,6 @@ class BoomAndRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAn } class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) - with HasRTCModuleImp with HasNoDebugModuleImp with HasPeripherySerialModuleImp with DontTouch From 612aa48e65c2441de46d87e02f8690e0e4826694 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 21:51:42 -0700 Subject: [PATCH 12/36] remove extra imports --- generators/example/src/main/scala/ConfigMixins.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 1380b90b..8e8f017b 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -4,17 +4,15 @@ import chisel3._ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.{XLen, MaxHartIdBits} +import freechips.rocketchip.tile.{XLen} import testchipip._ import sifive.blocks.devices.gpio._ -import boom.system.{BoomTilesKey} - /** * TODO: Why do we need this? */ From 6d622e7555f63fed80c7ed13e778b1b903be8ebe Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 22:00:04 -0700 Subject: [PATCH 13/36] add boomrocketexample to ci --- .circleci/config.yml | 72 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index 1e5146bb..50577af7 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -161,6 +161,40 @@ jobs: paths: - "/home/riscvuser/project" + prepare-boomrocketexample: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - verilator-installed-v1-{{ checksum "sims/verisim/verilator.mk" }} + + - run: + name: Building the boomrocketexample subproject using Verilator + command: .circleci/do-rtl-build.sh SUB_PROJECT=boomrocketexample CONFIG=SmallDefaultBoomAndRocketConfig + no_output_timeout: 120m + + - save_cache: + key: boomrocketexample-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project" + prepare-boom: docker: - image: riscvboom/riscvboom-images:0.0.5 @@ -319,6 +353,34 @@ jobs: name: Run boomexample benchmark tests command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig + boomrocketexample-run-benchmark-tests: + docker: + - image: riscvboom/riscvboom-images:0.0.5 + environment: + JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit + TERM: dumb + + steps: + # Checkout the code + - checkout + + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + + - restore_cache: + keys: + - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + + - restore_cache: + keys: + - boomrocketexample-{{ .Branch }}-{{ .Revision }} + + - run: + name: Run boomrocketexample benchmark tests + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomAndRocketConfig + boom-run-benchmark-tests: docker: - image: riscvboom/riscvboom-images:0.0.5 @@ -427,6 +489,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-boomrocketexample: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-boom: requires: - install-riscv-toolchain @@ -456,6 +523,11 @@ workflows: - install-riscv-toolchain - prepare-boomexample + - boomrocketexample-run-benchmark-tests: + requires: + - install-riscv-toolchain + - prepare-boomrocketexample + - boom-run-benchmark-tests: requires: - install-riscv-toolchain From f071b522b2b58b4e38041aacab19ddefc554fb2e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 22:01:50 -0700 Subject: [PATCH 14/36] ci harness fix for boomexample --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index fb4f3632..16e69d02 100644 --- a/variables.mk +++ b/variables.mk @@ -41,7 +41,7 @@ endif # for a BOOM based example system ifeq ($(SUB_PROJECT),boomexample) SBT_PROJECT ?= example - MODEL ?= BoomTestHarness + MODEL ?= BoomAndRocketTestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultBoomConfig From 5408d6ecbef7c7d972ce5c3fc3417a03739faaf2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 23 May 2019 22:58:28 -0700 Subject: [PATCH 15/36] bump boom --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 734d62c6..4b0365f4 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 734d62c6a91920f62730a4a076f8dfce29c52bf2 +Subproject commit 4b0365f4ff6eda6018b1f6fb116f54d0ace35486 From 4af9ea9846097305eec3cf0e56d4800dc3ca33f6 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 09:47:50 -0700 Subject: [PATCH 16/36] make default flags include timeout | all sims share flags --- common.mk | 4 ++-- variables.mk | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index f7e46608..3d67cebd 100644 --- a/common.mk +++ b/common.mk @@ -86,10 +86,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< && touch $@ + $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ ######################################################################################### # include build/project specific makefrags made from the generator diff --git a/variables.mk b/variables.mk index 0808003c..55c64871 100644 --- a/variables.mk +++ b/variables.mk @@ -147,7 +147,7 @@ output_dir=$(sim_dir)/output/$(long_name) # helper variables to run binaries ######################################################################################### BINARY ?= -SIM_FLAGS ?= +verbose +SIM_FLAGS ?= +verbose +max-cycles=$(timeout_cycles) sim_out_name = $(notdir $(basename $(BINARY))).$(long_name) ######################################################################################### From 08dd5b53758aadcc80845bba325f9fa10feea43b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 17:37:16 -0700 Subject: [PATCH 17/36] update boom to master --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 4b0365f4..92313af2 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 4b0365f4ff6eda6018b1f6fb116f54d0ace35486 +Subproject commit 92313af2a0ed4d8a93591a08f42ede1a0ffd808a From c341ffe57d96348e559b8b582858b19066b8266a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 21:22:46 -0700 Subject: [PATCH 18/36] remove verbose for default --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index 55c64871..7753e0ea 100644 --- a/variables.mk +++ b/variables.mk @@ -147,7 +147,7 @@ output_dir=$(sim_dir)/output/$(long_name) # helper variables to run binaries ######################################################################################### BINARY ?= -SIM_FLAGS ?= +verbose +max-cycles=$(timeout_cycles) +SIM_FLAGS ?= +max-cycles=$(timeout_cycles) sim_out_name = $(notdir $(basename $(BINARY))).$(long_name) ######################################################################################### From c19855bfa66406186738fac9363b08f2725f5f5c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 26 May 2019 15:46:19 -0700 Subject: [PATCH 19/36] shared heter-subsystem | single example SUB_PROJECT --- .circleci/config.yml | 8 +-- .../example/src/main/scala/ConfigMixins.scala | 66 ------------------- .../example/src/main/scala/Configs.scala | 12 ++-- .../example/src/main/scala/Generator.scala | 4 ++ .../example/src/main/scala/TestHarness.scala | 38 +---------- generators/example/src/main/scala/Top.scala | 65 +----------------- variables.mk | 26 +------- 7 files changed, 20 insertions(+), 199 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 50577af7..d2354fde 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -153,7 +153,7 @@ jobs: - run: name: Building the boomexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig no_output_timeout: 120m - save_cache: @@ -187,7 +187,7 @@ jobs: - run: name: Building the boomrocketexample subproject using Verilator - command: .circleci/do-rtl-build.sh SUB_PROJECT=boomrocketexample CONFIG=SmallDefaultBoomAndRocketConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig no_output_timeout: 120m - save_cache: @@ -351,7 +351,7 @@ jobs: - run: name: Run boomexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomConfig boomrocketexample-run-benchmark-tests: docker: @@ -379,7 +379,7 @@ jobs: - run: name: Run boomrocketexample benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomAndRocketConfig + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example CONFIG=SmallDefaultBoomAndRocketConfig boom-run-benchmark-tests: docker: diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 8e8f017b..dbfc1c34 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -41,72 +41,6 @@ class WithGPIO extends Config((site, here, up) => { GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) }) -// ---------------------------------------- -// Rocket Top Level System Parameter Mixins -// ---------------------------------------- - -/** - * Class to specify a "plain" top level rocket-chip system - */ -class WithNormalRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new RocketTop()(p)).module) - } -}) - -/** - * Class to specify a top level rocket-chip system with PWM - */ -class WithPWMRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new RocketTopWithPWMTL()(p)).module) -}) - -/** - * Class to specify a top level rocket-chip system with a PWM AXI4 - */ -class WithPWMAXI4RocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new RocketTopWithPWMAXI4()(p)).module) -}) - -/** - * Class to specify a top level rocket-chip system with a block device - */ -class WithBlockDeviceModelRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) - top.connectBlockDeviceModel() - top - } -}) - -/** - * Class to specify a top level rocket-chip system with a simulator block device - */ -class WithSimBlockDeviceRocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithBlockDevice()(p)).module) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -/** - * Class to specify a top level rocket-chip system with GPIO - */ -class WithGPIORocketTop extends Config((site, here, up) => { - case BuildRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new RocketTopWithGPIO()(p)).module) - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } -}) - // ----------------------------------------------- // BOOM + Rocket Top Level System Parameter Mixins // ----------------------------------------------- diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index ee17916f..98a37bc7 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -16,7 +16,7 @@ class BaseRocketConfig extends Config( new freechips.rocketchip.system.DefaultConfig) class DefaultRocketConfig extends Config( - new WithNormalRocketTop ++ + new WithNormalBoomAndRocketTop ++ new BaseRocketConfig) class HwachaConfig extends Config( @@ -28,26 +28,26 @@ class RoccRocketConfig extends Config( new DefaultRocketConfig) class PWMRocketConfig extends Config( - new WithPWMRocketTop ++ + new WithPWMBoomAndRocketTop ++ new BaseRocketConfig) class PWMAXI4RocketConfig extends Config( - new WithPWMAXI4RocketTop ++ + new WithPWMAXI4BoomAndRocketTop ++ new BaseRocketConfig) class SimBlockDeviceRocketConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceRocketTop ++ + new WithSimBlockDeviceBoomAndRocketTop ++ new BaseRocketConfig) class BlockDeviceModelRocketConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelRocketTop ++ + new WithBlockDeviceModelBoomAndRocketTop ++ new BaseRocketConfig) class GPIORocketConfig extends Config( new WithGPIO ++ - new WithGPIORocketTop ++ + new WithGPIOBoomAndRocketTop ++ new BaseRocketConfig) class DualCoreRocketConfig extends Config( diff --git a/generators/example/src/main/scala/Generator.scala b/generators/example/src/main/scala/Generator.scala index 3a1300b4..c5df8cb1 100644 --- a/generators/example/src/main/scala/Generator.scala +++ b/generators/example/src/main/scala/Generator.scala @@ -1,15 +1,19 @@ package example import scala.collection.mutable.LinkedHashSet + import chisel3._ import chisel3.experimental._ + import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} + import freechips.rocketchip.subsystem.{RocketTilesKey} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.{GeneratorApp} import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} + import boom.system.{BoomTilesKey, BoomTestSuites} object Generator extends GeneratorApp { diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index 3d488c1c..7bad5cbc 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -2,47 +2,13 @@ package example import chisel3._ import chisel3.experimental._ + import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} + import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp -// ------------------- -// Rocket Test Harness -// ------------------- - -case object BuildRocketTop extends Field[(Clock, Bool, Parameters) => RocketTopModule[RocketTop]] - -class RocketTestHarness(implicit val p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - // force Chisel to rename module - override def desiredName = "TestHarness" - - val dut = p(BuildRocketTop)(clock, reset.toBool, p) - dut.debug := DontCare - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - - io.success := dut.connectSimSerial() -} - // -------------------------- // BOOM + Rocket Test Harness // -------------------------- diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 59493492..ddd4a20f 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -1,76 +1,17 @@ package example import chisel3._ + import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util.DontTouch + import testchipip._ + import sifive.blocks.devices.gpio._ -// ------------------------ -// Rocket Top Level Systems -// ------------------------ - -class RocketTop(implicit p: Parameters) extends ExampleRocketSystem - with CanHaveMasterAXI4MemPort - with HasPeripheryBootROM - with HasNoDebug - with HasPeripherySerial { - override lazy val module = new RocketTopModule(this) -} - -class RocketTopModule[+L <: RocketTop](l: L) extends ExampleRocketSystemModuleImp(l) - with HasRTCModuleImp - with CanHaveMasterAXI4MemPortModuleImp - with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp - with DontTouch - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithPWMTL(implicit p: Parameters) extends RocketTop - with HasPeripheryPWMTL { - override lazy val module = new RocketTopWithPWMTLModule(this) -} - -class RocketTopWithPWMTLModule(l: RocketTopWithPWMTL) - extends RocketTopModule(l) with HasPeripheryPWMTLModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithPWMAXI4(implicit p: Parameters) extends RocketTop - with HasPeripheryPWMAXI4 { - override lazy val module = new RocketTopWithPWMAXI4Module(this) -} - -class RocketTopWithPWMAXI4Module(l: RocketTopWithPWMAXI4) - extends RocketTopModule(l) with HasPeripheryPWMAXI4ModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithBlockDevice(implicit p: Parameters) extends RocketTop - with HasPeripheryBlockDevice { - override lazy val module = new RocketTopWithBlockDeviceModule(this) -} - -class RocketTopWithBlockDeviceModule(l: RocketTopWithBlockDevice) - extends RocketTopModule(l) - with HasPeripheryBlockDeviceModuleImp - -//--------------------------------------------------------------------------------------------------------- - -class RocketTopWithGPIO(implicit p: Parameters) extends RocketTop - with HasPeripheryGPIO { - override lazy val module = new RocketTopWithGPIOModule(this) -} - -class RocketTopWithGPIOModule(l: RocketTopWithGPIO) - extends RocketTopModule(l) - with HasPeripheryGPIOModuleImp - // ------------------------------- // BOOM + Rocket Top Level Systems // ------------------------------- diff --git a/variables.mk b/variables.mk index 16e69d02..f73d7f7a 100644 --- a/variables.mk +++ b/variables.mk @@ -29,37 +29,13 @@ SUB_PROJECT ?= example ifeq ($(SUB_PROJECT),example) SBT_PROJECT ?= example - MODEL ?= RocketTestHarness + MODEL ?= BoomAndRocketTestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultRocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= RocketTop -endif -# for a BOOM based example system -ifeq ($(SUB_PROJECT),boomexample) - SBT_PROJECT ?= example - MODEL ?= BoomAndRocketTestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= $(SBT_PROJECT) - CONFIG ?= DefaultBoomConfig - CONFIG_PACKAGE ?= $(SBT_PROJECT) - GENERATOR_PACKAGE ?= $(SBT_PROJECT) - TB ?= TestDriver - TOP ?= BoomAndRocketTop -endif -# for a BOOM + Rocket based example system -ifeq ($(SUB_PROJECT),boomrocketexample) - SBT_PROJECT ?= example - MODEL ?= BoomAndRocketTestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= $(SBT_PROJECT) - CONFIG ?= DefaultBoomAndRocketConfig - CONFIG_PACKAGE ?= $(SBT_PROJECT) - GENERATOR_PACKAGE ?= $(SBT_PROJECT) - TB ?= TestDriver TOP ?= BoomAndRocketTop endif # for BOOM developers From dde22a969b2a2b167836d21dd5c0b5d7b0a077b8 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 15:29:09 -0700 Subject: [PATCH 20/36] add more to docs | 1st spelling pass | more links | proper formatting --- docs/Generators/BOOM.rst | 13 +- docs/Generators/Hwacha.rst | 8 + docs/Generators/Rocket.rst | 11 +- docs/Generators/index.rst | 10 +- .../Adding-An-Accelerator-Tutorial.rst | 216 ++++++++---------- .../Configs-Parameters-Mixins.rst | 64 ++++-- .../Getting-Started/Development-Ecosystem.rst | 25 ++ docs/Getting-Started/REBAR-Basics.rst | 110 +++++++++ docs/Getting-Started/ReBAR-Basics.rst | 86 ------- docs/Getting-Started/Running-A-Simulation.rst | 144 +++++------- docs/Getting-Started/index.rst | 8 +- .../rebar-generator-mixins.rst | 6 +- docs/Makefile | 4 +- docs/Simulation/Commercial-Simulators.rst | 38 +-- docs/Simulation/FPGA-Based-Simulators.rst | 12 +- docs/Simulation/Open-Source-Simulators.rst | 38 +-- docs/Simulation/index.rst | 6 +- docs/Tools/Barstools.rst | 4 +- docs/Tools/Chisel.rst | 18 +- docs/Tools/FIRRTL.rst | 9 + docs/Tools/index.rst | 3 +- docs/VLSI/HAMMER.rst | 7 + docs/VLSI/index.rst | 5 +- docs/conf.py | 14 +- docs/index.rst | 41 +--- 25 files changed, 471 insertions(+), 429 deletions(-) create mode 100644 docs/Generators/Hwacha.rst create mode 100644 docs/Getting-Started/Development-Ecosystem.rst create mode 100644 docs/Getting-Started/REBAR-Basics.rst delete mode 100644 docs/Getting-Started/ReBAR-Basics.rst create mode 100644 docs/VLSI/HAMMER.rst diff --git a/docs/Generators/BOOM.rst b/docs/Generators/BOOM.rst index f0cac535..e04bed8f 100644 --- a/docs/Generators/BOOM.rst +++ b/docs/Generators/BOOM.rst @@ -1,10 +1,11 @@ Berkeley Out-of-Order Machine (BOOM) ============================================== -The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. +The `Berkeley Out-of-Order Machine (BOOM) `__ is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. +It serves as a drop-in replacement to the Rocket core given by Rocket Chip. +BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 outoforder processors. +Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”). +Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. +However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). -BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 outoforder processors. Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”). - -Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). - -Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages __`. +Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages __`. diff --git a/docs/Generators/Hwacha.rst b/docs/Generators/Hwacha.rst new file mode 100644 index 00000000..d040d35d --- /dev/null +++ b/docs/Generators/Hwacha.rst @@ -0,0 +1,8 @@ +Hwacha +==================================== + +The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption. +Inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures Scale and Maven, we are bringing back elegant, performant, and energy-efficient aspects of vector processing to modern data-parallel architectures. +We propose a new vector-fetch architectural paradigm, which focuses on the following aspects for higher performance, better energy efficiency, and lower complexity. + +For more information, please visit the `Hwacha website `__. diff --git a/docs/Generators/Rocket.rst b/docs/Generators/Rocket.rst index 06bf26eb..401b9e36 100644 --- a/docs/Generators/Rocket.rst +++ b/docs/Generators/Rocket.rst @@ -1,3 +1,12 @@ Rocket ==================================== -TODO: Basic rocket introduction + +`Rocket `__ is a 5-stage in-order scalar core generator that is supported by `SiFive `__. +It supports the open source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language. +It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction. +Branch prediction is configurable and provided by a branch target buffer (BTB), branch history table (BHT), and a return address stack (RAS). +For floating-point, Rocket makes use of Berkeley’s Chisel implementations of floating-point units. +Rocket also supports the RISC-V machine, supervisor, and user privilege levels. +A number of parameters are exposed, including the optional support of some ISA extensions (M, A, F, D), the number of floating-point pipeline stages, and the cache and TLB sizes. + +For more information, please refer to the `GitHub repository `__, `technical report `__ or to `this Chisel Community Conference video `__. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 7aa22141..765b2549 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -1,8 +1,11 @@ Generators ============================ -Generator can be thought of as generalized RTL designs, written using a mix of meta-programming and standard RTL. -This type of meta-programming is enabled by the Chisel hardware description framework embedded in Scala. -A standard RTL design is esentially a degenerate form of a generator. However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. The following pages introduce the generators integrated with the ReBAR framework. + +Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL. +This type of meta-programming is enabled by the Chisel hardware description language (see :ref:`Chisel`). +A standard RTL design is essentially just a single instance of a design coming from a generator. +However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. +The following pages introduce the generators integrated with the REBAR framework. .. toctree:: :maxdepth: 2 @@ -10,4 +13,5 @@ A standard RTL design is esentially a degenerate form of a generator. However, b Rocket BOOM + Hwacha diff --git a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst index 1df6b0d5..6b4c58c5 100644 --- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst +++ b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst @@ -1,80 +1,69 @@ - - Adding An Accelerator/Device =============================== Accelerators or custom IO devices can be added to your SoC in several ways: -+ MMIO Peripheral (a.k.a TileLink-Attached Accelerator) -+ Tightly-Coupled RoCC Accelerator -These approaches differ in the method of the communication between the processor and the custom block. +* MMIO Peripheral (a.k.a TileLink-Attached Accelerator) +* Tightly-Coupled RoCC Accelerator -With the TileLink-Attached approach, the processor communicates with MMIO peripherals through memory-mapped registers. +These approaches differ in the method of the communication between the processor and the custom block. -In contrast, the processor communicates with a RoCC accelerators through a custom protocol and custom non-standard ISA instructions reserved in the RISC-V ISA encoding space. Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU. +With the TileLink-Attached approach, the processor communicates with MMIO peripherals through memory-mapped registers. + +In contrast, the processor communicates with a RoCC accelerators through a custom protocol and custom non-standard ISA instructions reserved in the RISC-V ISA encoding space. +Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU. RoCC coprocessor instructions have the following form. -:: +.. code-block:: customX rd, rs1, rs2, funct -The X will be a number 0-3, and determines the opcode of the instruction, -which controls which accelerator an instruction will be routed to. -The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination -register and two source registers. The ``funct`` field is a 7-bit integer that -the accelerator can use to distinguish different instructions from each other. - -Note that communication through a RoCC interfaces requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with approriate driver support. +The X will be a number 0-3, and determines the opcode of the instruction, which controls which accelerator an instruction will be routed to. +The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination register and two source registers. +The ``funct`` field is a 7-bit integer that the accelerator can use to distinguish different instructions from each other. +Note that communication through a RoCC interface requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with approriate driver support. Integrating into the Generator Build System ------------------------------------------- -While developing, you want to include Chisel code in a submodule so that it -can be shared by different projects. To add a submodule to the project -template, make sure that your project is organized as follows. +While developing, you want to include Chisel code in a submodule so that it can be shared by different projects. +To add a submodule to the REBAR framework, make sure that your project is organized as follows. +.. code-block:: yourproject/ build.sbt src/main/scala/ YourFile.scala -Put this in a git repository and make it accessible. Then add it as a submodule -to under the following directory hierarchy: ``rebar/generators/yourproject``. +Put this in a git repository and make it accessible. +Then add it as a submodule to under the following directory hierarchy: ``generators/yourproject``. -:: +.. code-block:: shell + cd generators/ git submodule add https://git-repository.com/yourproject.git -Then add `yourproject` to the ReBAR top-level build.sbt file. +Then add ``yourproject`` to the REBAR top-level build.sbt file. -:: +.. code-block:: scala lazy val yourproject = project.settings(commonSettings).dependsOn(rocketchip) - You can then import the classes defined in the submodule in a new project if you add it as a dependency. For instance, if you want to use this code in -the `example` project, change the final line in build.sbt to the following. +the ``example`` project, change the final line in build.sbt to the following. -:: +.. code-block:: scala lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) - -Finally, add `yourproject` to the `PACKAGES` variable in the `Makefrag`. This will allow make to detect -that your source files have changed when building the verilog/firrtl files. - - +Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the REBAR top level. +This will allow make to detect that your source files have changed when building the Verilog/FIRRTL files. MMIO Peripheral ------------------ -The easiest way to create a TileLink peripheral is to use the -TLRegisterRouter, which abstracts away the details of handling the TileLink -protocol and provides a convenient interface for specifying memory-mapped -registers. To create a RegisterRouter-based peripheral, you will need to -specify a parameter case class for the configuration settings, a bundle trait -with the extra top-level ports, and a module implementation containing the -actual RTL. +The easiest way to create a TileLink peripheral is to use the ``TLRegisterRouter``, which abstracts away the details of handling the TileLink protocol and provides a convenient interface for specifying memory-mapped registers. +To create a RegisterRouter-based peripheral, you will need to specify a parameter case class for the configuration settings, a bundle trait with the extra top-level ports, and a module implementation containing the actual RTL. -:: +.. code-block:: scala case class PWMParams(address: BigInt, beatBytes: Int) trait PWMTLBundle extends Bundle { @@ -103,16 +92,12 @@ actual RTL. } -Once you have these classes, you can construct the final peripheral by -extending the TLRegisterRouter and passing the proper arguments. The first -set of arguments determines where the register router will be placed in the -global address map and what information will be put in its device tree entry. -The second set of arguments is the IO bundle constructor, which we create -by extending TLRegBundle with our bundle trait. The final set of arguments -is the module constructor, which we create by extends TLRegModule with our -module trait. +Once you have these classes, you can construct the final peripheral by extending the ``TLRegisterRouter`` and passing the proper arguments. +The first set of arguments determines where the register router will be placed in the global address map and what information will be put in its device tree entry. +The second set of arguments is the IO bundle constructor, which we create by extending ``TLRegBundle`` with our bundle trait. +The final set of arguments is the module constructor, which we create by extends ``TLRegModule`` with our module trait. -:: +.. code-block:: scala class PWMTL(c: PWMParams)(implicit p: Parameters) extends TLRegisterRouter( c.address, "pwm", Seq("ucbbar,pwm"), @@ -120,20 +105,17 @@ module trait. new TLRegBundle(c, _) with PWMTLBundle)( new TLRegModule(c, _, _) with PWMTLModule) +The full module code can be found in ``generators/example/src/main/scala/PWM.scala``. -The full module code with comments can be found in src/main/scala/example/PWM.scala. +After creating the module, we need to hook it up to our SoC. +Rocket Chip accomplishes this using the cake pattern. +This basically involves placing code inside traits. +In the Rocket Chip cake, there are two kinds of traits: a ``LazyModule`` trait and a module implementation trait. -After creating the module, we need to hook it up to our SoC. Rocketchip -accomplishes this using the [cake pattern](http://www.cakesolutions.net/teamblogs/2011/12/19/cake-pattern-in-depth). -This basically involves placing code inside traits. In the RocketChip cake, -there are two kinds of traits: a LazyModule trait and a module implementation -trait. +The ``LazyModule`` trait runs setup code that must execute before all the hardware gets elaborated. +For a simple memory-mapped peripheral, this just involves connecting the peripheral's TileLink node to the MMIO crossbar. -The LazyModule trait runs setup code that must execute before all the hardware -gets elaborated. For a simple memory-mapped peripheral, this just involves -connecting the peripheral's TileLink node to the MMIO crossbar. - -:: +.. code-block:: scala trait HasPeripheryPWM extends HasSystemNetworks { implicit val p: Parameters @@ -147,17 +129,15 @@ connecting the peripheral's TileLink node to the MMIO crossbar. } -Note that the PWMTL class we created from the register router is itself a -LazyModule. Register routers have a TileLike node simply named "node", which -we can hook up to the RocketChip peripheryBus. This will automatically add -address map and device tree entries for the peripheral. +Note that the ``PWMTL`` class we created from the register router is itself a ``LazyModule``. +Register routers have a TileLike node simply named "node", which we can hook up to the Rocket Chip bus. +This will automatically add address map and device tree entries for the peripheral. -The module implementation trait is where we instantiate our PWM module and -connect it to the rest of the SoC. Since this module has an extra `pwmout` -output, we declare that in this trait, using Chisel's multi-IO -functionality. We then connect the PWMTL's pwmout to the pwmout we declared. +The module implementation trait is where we instantiate our PWM module and connect it to the rest of the SoC. +Since this module has an extra `pwmout` output, we declare that in this trait, using Chisel's multi-IO functionality. +We then connect the ``PWMTL``'s pwmout to the pwmout we declared. -:: +.. code-block:: scala trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp { implicit val p: Parameters val outer: HasPeripheryPWM @@ -167,11 +147,10 @@ functionality. We then connect the PWMTL's pwmout to the pwmout we declared. pwmout := outer.pwm.module.io.pwmout } +Now we want to mix our traits into the system as a whole. +This code is from ``generators/example/src/main/scala/Top.scala``. -Now we want to mix our traits into the system as a whole. This code is from -src/main/scala/example/Top.scala. - -:: +.. code-block:: scala class ExampleTopWithPWM(q: Parameters) extends ExampleTop(q) with PeripheryPWM { override lazy val module = Module( @@ -182,19 +161,15 @@ src/main/scala/example/Top.scala. extends ExampleTopModule(l) with HasPeripheryPWMModuleImp -Just as we need separate traits for LazyModule and module implementation, we -need two classes to build the system. The ExampleTop classes already have the -basic peripherals included for us, so we will just extend those. +Just as we need separate traits for ``LazyModule`` and module implementation, we need two classes to build the system. +The ``ExampleTop`` classes already have the basic peripherals included for us, so we will just extend those. -The ExampleTop class includes the pre-elaboration code and also a lazy val to -produce the module implementation (hence LazyModule). The ExampleTopModule -class is the actual RTL that gets synthesized. +The ``ExampleTop`` class includes the pre-elaboration code and also a ``lazy val`` to produce the module implementation (hence ``LazyModule``). +The ``ExampleTopModule`` class is the actual RTL that gets synthesized. -Finally, we need to add a configuration class in -src/main/scala/example/Configs.scala that tells the TestHarness to instantiate -ExampleTopWithPWM instead of the default ExampleTop. +Finally, we need to add a configuration class in ``generators/example/src/main/scala/Configs.scala`` that tells the ``TestHarness`` to instantiate ``ExampleTopWithPWM`` instead of the default ``ExampleTop``. -:: +.. code-block:: scala class WithPWM extends Config((site, here, up) => { case BuildTop => (p: Parameters) => Module(LazyModule(new ExampleTopWithPWM()(p)).module) @@ -203,9 +178,9 @@ ExampleTopWithPWM instead of the default ExampleTop. class PWMConfig extends Config(new WithPWM ++ new BaseExampleConfig) -Now we can test that the PWM is working. The test program is in tests/pwm.c +Now we can test that the PWM is working. The test program is in ``tests/pwm.c``. -:: +.. code-block:: c #define PWM_PERIOD 0x2000 #define PWM_DUTY 0x2008 #define PWM_ENABLE 0x2010 @@ -230,29 +205,26 @@ Now we can test that the PWM is working. The test program is in tests/pwm.c } -This just writes out to the registers we defined earlier. The base of the -module's MMIO region is at 0x2000. This will be printed out in the address -map portion when you generated the verilog code. +This just writes out to the registers we defined earlier. +The base of the module's MMIO region is at 0x2000. +This will be printed out in the address map portion when you generated the verilog code. -Compiling this program with make produces a `pwm.riscv` executable. +Compiling this program with make produces a ``pwm.riscv`` executable. Now with all of that done, we can go ahead and run our simulation. -:: +.. code-block:: shell cd verisim make CONFIG=PWMConfig ./simulator-example-PWMConfig ../tests/pwm.riscv - - - Adding a RoCC Accelerator ---------------------------- -RoCC accelerators are lazy modules that extend the LazyRoCC class. -Their implementation should extends the LazyRoCCModule class. +RoCC accelerators are lazy modules that extend the ``LazyRoCC`` class. +Their implementation should extends the ``LazyRoCCModule`` class. -:: +.. code-block:: scala class CustomAccelerator(opcodes: OpcodeSet) (implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new CustomAcceleratorModule(this) @@ -277,34 +249,30 @@ Their implementation should extends the LazyRoCCModule class. } -The ``opcodes`` parameter for ``LazyRoCC`` is -the set of custom opcodes that will map to this accelerator. More on this -in the next subsection. +The ``opcodes`` parameter for ``LazyRoCC`` is the set of custom opcodes that will map to this accelerator. +More on this in the next subsection. The ``LazyRoCC`` class contains two TLOutputNode instances, ``atlNode`` and ``tlNode``. -The former connects into a tile-local arbiter along with the backside of the -L1 instruction cache. The latter connects directly to the L1-L2 crossbar. -The corresponding Tilelink ports in the module implementation's IO bundle -are ``atl`` and ``tl``, respectively. +The former connects into a tile-local arbiter along with the backside of the L1 instruction cache. +The latter connects directly to the L1-L2 crossbar. +The corresponding Tilelink ports in the module implementation's IO bundle are ``atl`` and ``tl``, respectively. -The other interfaces available to the accelerator are ``mem``, which provides -access to the L1 cache; ``ptw`` which provides access to the page-table walker; -the ``busy`` signal, which indicates when the accelerator is still handling an -instruction; and the ``interrupt`` signal, which can be used to interrupt the CPU. +The other interfaces available to the accelerator are ``mem``, which provides access to the L1 cache; +``ptw`` which provides access to the page-table walker; +the ``busy`` signal, which indicates when the accelerator is still handling an instruction; +and the ``interrupt`` signal, which can be used to interrupt the CPU. -Look at the examples in rocket-chip/src/main/scala/tile/LazyRocc.scala for -detailed information on the different IOs. +Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRocc.scala`` for detailed information on the different IOs. -### Adding RoCC accelerator to Config +Adding RoCC accelerator to Config +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -RoCC accelerators can be added to a core by overriding the ``BuildRoCC`` parameter -in the configuration. This takes a sequence of functions producing ``LazyRoCC`` -objects, one for each accelerator you wish to add. +RoCC accelerators can be added to a core by overriding the ``BuildRoCC`` parameter in the configuration. +This takes a sequence of functions producing ``LazyRoCC`` objects, one for each accelerator you wish to add. -For instance, if we wanted to add the previously defined accelerator and -route custom0 and custom1 instructions to it, we could do the following. +For instance, if we wanted to add the previously defined accelerator and route custom0 and custom1 instructions to it, we could do the following. -:: +.. code-block:: scala class WithCustomAccelerator extends Config((site, here, up) => { case BuildRoCC => Seq((p: Parameters) => LazyModule( new CustomAccelerator(OpcodeSet.custom0 | OpcodeSet.custom1)(p))) @@ -313,17 +281,13 @@ route custom0 and custom1 instructions to it, we could do the following. class CustomAcceleratorConfig extends Config( new WithCustomAccelerator ++ new DefaultExampleConfig) - - - Adding a DMA port ------------------- -IO devices or accelerators (like a disk or network -driver), we may want to have the device write directly to the coherent -memory system instead. To add a device like that, you would do the following. +IO devices or accelerators (like a disk or network driver), we may want to have the device write directly to the coherent memory system instead. +To add a device like that, you would do the following. -:: +.. code-block:: scala class DMADevice(implicit p: Parameters) extends LazyModule { val node = TLClientNode(TLClientParameters( name = "dma-device", sourceId = IdRange(0, 1))) @@ -355,8 +319,6 @@ memory system instead. To add a device like that, you would do the following. The ``ExtBundle`` contains the signals we connect off-chip that we get data from. -The DMADevice also has a Tilelink client port that we connect into the L1-L2 -crossbar through the front-side buffer (fsb). The sourceId variable given in -the TLClientNode instantiation determines the range of ids that can be used -in acquire messages from this device. Since we specified [0, 1) as our range, -only the ID 0 can be used. +The DMADevice also has a Tilelink client port that we connect into the L1-L2 crossbar through the front-side buffer (fsb). +The sourceId variable given in the ``TLClientNode`` instantiation determines the range of ids that can be used in acquire messages from this device. +Since we specified [0, 1) as our range, only the ID 0 can be used. diff --git a/docs/Getting-Started/Configs-Parameters-Mixins.rst b/docs/Getting-Started/Configs-Parameters-Mixins.rst index b87a47c1..852f85af 100644 --- a/docs/Getting-Started/Configs-Parameters-Mixins.rst +++ b/docs/Getting-Started/Configs-Parameters-Mixins.rst @@ -1,55 +1,62 @@ Configs, Parameters, Mix-ins, and Everything In Between ======================================================== -A significant portion of generators in the ReBAR framework use the Rocket chip parameter system. +A significant portion of generators in the REBAR framework use the Rocket Chip parameter system. This parameter system enables for the flexible configuration of the SoC without invasive RTL changes. In order to use the parameter system correctly, we will use several terms and conventions: -Parameter +Parameters -------------------- + TODO: Need to explain up, site, field, and other stuff from Henry's thesis. -It is important to note that a significant challenge with the Rocket parameter system is being able to identify the correct parameter to use, and the impact that parameter has on the overall system. We are still investigating methods to facilitate parameter exploration and discovery. +It is important to note that a significant challenge with the Rocket parameter system is being able to identify the correct parameter to use, and the impact that parameter has on the overall system. +We are still investigating methods to facilitate parameter exploration and discovery. - -Config +Configs --------------------- -A `Config` is a collection of multiple parameters being set to specific values. -Configs are additive, and can override each other. -A Config can be composed of other configs. -The naming convetion for an additive config is ``With``, while the naming convention for a non-additive config will be ````. -Configs can take arguments which will in-turn set parameters in the specific configs. -Example config: +A *Config* is a collection of multiple generator parameters being set to specific values. +Configs are additive, can override each other, and can be composed of other Configs. +The naming convention for an additive Config is ``With``, while the naming convention for a non-additive Config will be ````. +Configs can take arguments which will in-turn set parameters in the design or reference other parameters in the design (see :ref:`Parameters`). +:numref:`basic-config-example` shows a basic additive Config class that takes in zero arguments and instead uses hardcoded values to set the RTL design parameters. +In this example, ``MyAcceleratorConfig`` is a Scala case class that defines a set of variables that the generator can use when referencing the ``MyAcceleratorKey`` in the design. + +.. _basic-config-example: .. code-block:: scala class WithMyAcceleratorParams extends Config((site, here, up) => { + case BusWidthBits => 128 case MyAcceleratorKey => MyAcceleratorConfig( - Rows = 2, + rows = 2, rowBits = 64, - Columns = 16, + columns = 16, hartId = 1, - some_length = 256, - ) + someLength = 256) }) -Example config which uses a higher level config: +This next example (:numref:`complex-config-example`) shows a "higher-level" additive Config that uses prior parameters that were set to derive other parameters. +.. _complex-config-example: .. code-block:: scala class WithMyMoreComplexAcceleratorConfig extends Config((site, here, up) => { + case BusWidthBits => 128 case MyAcceleratorKey => MyAcceleratorConfig( Rows = 2, rowBits = site(SystemBusKey).beatBits, - hartId = up(RocketTilesKey, site).length, - ) + hartId = up(RocketTilesKey, site).length) }) -Example of additive configs: +:numref:`top-level-config` shows a non-additive Config that combines the prior two additive Configs using ``++``. +The additive Configs are applied from the right to left in the list (or bottom to top in the example). +Thus, the order of the parameters being set will first start with the ``DefaultExampleConfig``, then ``WithMyAcceleratorParams``, then ``WithMyMoreComplexAcceleratorConfig``. +.. _top-level-config: .. code-block:: scala class SomeAdditiveConfig extends Config( @@ -58,13 +65,15 @@ Example of additive configs: new DefaultExampleConfig ) - Cake Pattern ------------------------- -The cake pattern is a scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes refered to as dependancy injection). It is used in the Rocket chip SoC library and ReBAR framework in merging multiple system components and IO interfaces into a large system component. -Example of using the cake pattern to merge multiple system components into a single top-level design, extending a basic Rocket SoC: +A cake pattern is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection). +It is used in the Rocket Chip SoC library and REBAR framework in merging multiple system components and IO interfaces into a large system component. +:numref:`cake-example` shows a Rocket Chip based SoC that merges multiple system components (BootROM, UART, etc) into a single top-level design. + +.. _cake-example: .. code-block:: scala class MySoC(implicit p: Parameters) extends RocketSubsystem @@ -78,9 +87,14 @@ Example of using the cake pattern to merge multiple system components into a sin //Additional top-level specific instantiations or wiring } - Mix-in --------------------------- -A mix-in is a scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. -The naming convetion for an additive mix-in is ``Has``. +A mix-in is a Scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. +The naming convention for an additive mix-in is ``Has``. +This is show in :numref:`cake-example` where things such as ``HasPeripherySerial`` connect a RTL component to a bus and expose signals to the top-level. + +Additional References +--------------------------- + +A brief explanation of some of these topics is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY. diff --git a/docs/Getting-Started/Development-Ecosystem.rst b/docs/Getting-Started/Development-Ecosystem.rst new file mode 100644 index 00000000..8946a319 --- /dev/null +++ b/docs/Getting-Started/Development-Ecosystem.rst @@ -0,0 +1,25 @@ +Development Ecosystem +=============================== + +REBAR Approach +------------------------------------------- + +The trend towards agile hardware design and evaluation provides an ecosystem of debugging and implementation tools, that make it easier for computer architecture researchers to develop novel concepts. +REBAR hopes to build on this prior work in order to create a singular location to which multiple projects within the `Berkeley Architecture Research `__ can coexist and be used together. +REBAR aims to be the "one-stop shop" for creating and testing your own unique System on a Chip (SoC). + +Chisel/FIRRTL +------------------------------------------- + +One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language `__ and the `FIRRTL Compiler `__. +Chisel is an embedded language within Scala that provides a set of libraries to help hardware designers create highly parameterizable RTL. +FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimation, circuit analysis, connectivity checks, and much more! +These two tools in combination allow quick design space exploration and development of new RTL. + +Generators +------------------------------------------- + +Within this repository, all of the Chisel RTL is written as generators. +Generators are parametrized programs designed to generate RTL code based on configuration specifications. +Generators can be used to generate Systems-on-Chip (SoCs) using a collection of system components organized in unique generator projects. +Generators allow you to create a family of SoC designs instead of a single instance of a design! diff --git a/docs/Getting-Started/REBAR-Basics.rst b/docs/Getting-Started/REBAR-Basics.rst new file mode 100644 index 00000000..69963b3e --- /dev/null +++ b/docs/Getting-Started/REBAR-Basics.rst @@ -0,0 +1,110 @@ +REBAR Basics +=============================== + +Generators +------------------------------------------- + +The REBAR Framework currently consists of the following RTL generators: + +Processor Cores +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +**Rocket** + An in-order RISC-V core. + See :ref:`Rocket` for more information. + +**BOOM (Berkeley Out-of-Order Machine)** + An out-of-order RISC-V core. + See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. + +Data-Parallel Accelerators +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +**Hwacha** + A decoupled vector architecture co-processor. + Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model. + Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface. + See :ref:`Hwacha` for more information. + +System Components: +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +**icenet** + A Network Interface Controller (NIC) designed to achieve up to 200 Gbps. + +**sifive-blocks** + System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator. + These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices. + +**AWL (Analog Widget Library)** + Digital components required for integration with high speed serial links. + +**testchipip** + A collection of utilities used for testing chips and interfacing them with larger test environments. + +.. Fixed Function Accelerators: + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + TBD + +Tools +------------------------------------------- + +**Chisel** + A hardware description library embedded in Scala. + Chisel is used to write RTL generators using meta-programming, by embedding hardware generation primitives in the Scala programming language. + The Chisel compiler elaborates the generator into a FIRRTL output. + See :ref:`Chisel` for more information. + +**FIRRTL** + An intermediate representation library for RTL description of digital designs. + FIRRTL is used as a formalized digital circuit representation between Chisel and Verilog. + FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation. + See :ref:`FIRRTL` for more information. + +**Barstools** + A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL. + See :ref:`Barstools` for more information. + +Toolchains +------------------------------------------- + +**riscv-tools** + A collection of software toolchains used to develop and execute software on the RISC-V ISA. + The include compiler and assembler toolchains, functional ISA simulator (spike), the Berkeley Boot Loader (BBL) and proxy kernel. + The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.). + Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the REBAR framework. + +**esp-tools** + A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension. + This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.) + +Sims +------------------------------------------- + +**verisim (Verilator wrapper)** + Verilator is an open source Verilog simulator. + The ``verisim`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). + See :ref:`Verilator` for more information. + +**vsim (VCS wrapper)** + VCS is a proprietary Verilog simulator. + Assuming the user has valid VCS licenses and installations, the ``vsim`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). + See :ref:`VCS` for more information. + +**FireSim** + FireSim is an open-source FPGA-accelerated simulation platform, using Amazon Web Services (AWS) EC2 F1 instances on the public cloud. + FireSim automatically transforms and instruments open-hardware designs into fast (10s-100s MHz), deterministic, FPGA-based simulators that enable productive pre-silicon verification and performance validation. + To model I/O, FireSim includes synthesizeable and timing-accurate models for standard interfaces like DRAM, Ethernet, UART, and others. + The use of the elastic public cloud enable FireSim to scale simulations up to thousands of nodes. + In order to use FireSim, the repository must be cloned and executed on AWS instances. + See :ref:`FireSim` for more information. + +VLSI +------------------------------------------- + +**HAMMER** + HAMMER is a VLSI flow designed to provide a layer of abstraction between general physical design concepts to vendor-specific EDA tool commands. + The HAMMER flow provide automated scripts which generate relevant tool commands based on a higher level description of physical design constraints. + The HAMMER flow also allows for re-use of process technology knowledge by enabling the construction of process-technology-specific plug-ins, which describe particular constraints relating to that process technology (obsolete standard cells, metal layer routing constraints, etc.). + The HAMMER flow requires access to proprietary EDA tools and process technology libraries. + See :ref:`HAMMER` for more information. diff --git a/docs/Getting-Started/ReBAR-Basics.rst b/docs/Getting-Started/ReBAR-Basics.rst deleted file mode 100644 index eb54033e..00000000 --- a/docs/Getting-Started/ReBAR-Basics.rst +++ /dev/null @@ -1,86 +0,0 @@ - - -ReBAR Basics -=============================== - - -Generators -------------------------------------------- -Generators are parametrized programs written as RTL code, designed to generate verilog code based on configuration specifications. -Generators can be used to generate Systems-on-Chip (SoCs) using a collection of system components organized in unique generator projects. -The ReBAR Framework currently consists of the following generators: - -Processor Cores -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**Rocket** - An in-order RISC-V core. - -**BOOM (Berkeley Out-of-Order Machine)** - An out-of-order RISC-V core. - -Data-Parallel Accelerators -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**Hwacha** - A decoupled vector architecture co-processor. Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model. - Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface - - -System Components: -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**icenet** - A Network Interface Controller (NIC) designed to achieve up to 200 Gbps. - -**sifive-blocks** - System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket chip generator. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices. - -**AWL (Analog Widget Library)** - Digital components required for integration with high speed serial links. - -**testchipip** - A collection of utilites used for testing chips and interfacing them with larger test environments. - - -Fixed Function Accelerators: -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -TBD - - - -Tools -------------------------------------------- -**Chisel** - A hardware description library embedded in Scala. Chisel is used to write RTL generators using meta-programming, by emdedding hardware generation primitives in the Scala programming language. The Chisel compilter elaborate the generator into a FIRRTL output. - -**FIRRTL** - An intermediate representation library for RTL description of digital designs. FIRRTL is used as a formalized digital circuit representation between Chisel and Verilog. FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation. - -**BARSTOOLS** - A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL. - - -Toolchains -------------------------------------------- -**riscv-tools** - A collection of software toolchains used to develope and execute software on the RISC-V ISA. The include compiler and assembler toolchains, functional ISA simulator (spike), the Berkeley Boot Loader (BBL) and proxy kernel. The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.). Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the ReBAR framework. - - -**esp-tools** - A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension. This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.) - - -Sims -------------------------------------------- -**verisim (Verilator wrapper)** - Verilator is an open source Verilog simulator. The verisim directory provides wrappers which construct verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). - -**vsim (VCS wrapper)** - VCS is a proprietary Verilog simulator. Assuming the user has valid VCS licenses and installations, the vsim directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). - -**FireSim** - FireSim is an open-source FPGA-accelerated simulation platform, using Amazon Web Services (AWS) EC2 F1 instances on the public cloud. FireSim automatically transforms and instruments open-hardware designs into fast (10s-100s MHz), deterministic, FPGA-based simulators that enable productive pre-silicon verification and performance validation. To model I/O, FireSim includes synthesizeable and timing-accurate models for standard interfaces like DRAM, Ethernet, UART, and others. The use of the elastic public clound enable FireSim to scale simulations up to thousands of nodes. In order to use FireSim, the repository must be cloned and executed on AWS instances. - - -VLSI -------------------------------------------- -**HAMMER** - HAMMER is a VLSI flow designed to provide a layer of abstraction between general physical design concepts to vendor-specific EDA tool commands. The HAMMER flow provide automated scripts which generate relevant tool commands based on a higher level description of physical desing contraints. The HAMMER flow also allows for re-use of process technology knowledge by enabling the construction of process-technology-specific plug-ins, which describe particular contraints relating to that process technology (obsolete standard cells, metal layer routing contraints, etc.). The HAMMER flow requires access to proprietry EDA tools and process technology libraries. diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index a86eb7e8..e67b3813 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -1,123 +1,103 @@ Running A Simulation ======================================================== -ReBAR provides support and intergration for multiple simulation flows, for various user levels and requirments. -In the majority of cases during a digital design development process, simple software RTL. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. - +REBAR provides support and integration for multiple simulation flows, for various user levels and requirements. +In the majority of cases during a digital design development process, simple software RTL simulation is needed. +When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. Software RTL Simulation ------------------------ -The ReBAR framework provides wrappers for two common software RTL simulators: the open-source Verilator simulator. and the proprietry VCS simulator.The following instructions assume at least one of these simulators is installed. +The REBAR framework provides wrappers for two common software RTL simulators: +the open-source Verilator simulator and the proprietary VCS simulator. +For more information on either of these simulators, please refer to :ref:`Verilator` or :ref:`VCS`. +The following instructions assume at least one of these simulators is installed. -Verilator +Verilator/VCS Flows ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -Verilator is an open-source RTL simulator. We run Verilator simulations from within the ``sims/verisim`` directory. Therefore, we will start by entering that directory: +Verilator is an open-source RTL simulator. +We run Verilator simulations from within the ``sims/verisim`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations. +On the other hand, VCS is a proprietary RTL simulator. +We run VCS simulations from within the ``sims/vsim`` directory. +Assuming VCS is already installed on the machine running simulations (and is found on our ``PATH``), then this guide is the same for both Verilator and VCS. + +First, we will start by entering the Verilator or VCS directory: .. code-block:: shell - cd sims/verisim + # Enter Verilator directory + cd sims/verisim -In order to construct the simulator with our custom design, we run the following command within the ``sims/verisim`` directory: + # OR + + # Enter VCS directory + cd sims/vsim + +In order to construct the simulator with our custom design, we run the following command within the simulator directory: .. code-block:: shell - make TOP= CONFIG= SBT_PROJECT= MODEL= + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... -Where ```` is the class name of the top level design, ```` is the name of the class we create for our parameters configuration, ```` is the name of the sbt package the include both our top-level class and our config class, and ```` is the name of the class which defines the test harness for our system. -The ``make`` command may have additional parameters (such as ``CONFIG_PACKAGE`` or ``MODEL_PACKAGE``) depending on the complexity of the design and integration with multiple sub-project repositories in the sbt-based build system. +Each of these make variables correspond to a particular part of the design/codebase and are needed so that the make system can correctly build and make a RTL simulation. +The ``SBT_PROJECT`` is the ``build.sbt`` project that holds all of the source files and that will be run during the RTL build. +The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design. +Normally, these are the same, but in some cases these can differ (if the Chisel class differs than what is emitted in the Verilog). +The ``MODEL_PACKAGE`` is the Scala package (in the Scala code that says ``package ...``) that holds the ``MODEL`` class. +The ``CONFIG`` is the name of the class used for the parameter Config while the ``CONFIG_PACKAGE`` is the Scala package it resides in. +The ``GENERATOR_PACKAGE`` is the Scala package that holds the Generator class that elaborates the design. +The ``TB`` is the name of the Verilog wrapper that connects the ``TestHarness`` to VCS/Verilator for simulation. +Finally, the ``TOP`` variable is used to distinguish between the top-level of the design and the ``TestHarness`` in our system. +For example, in the normal case, the ``MODEL`` variable specifies the ``TestHarness`` as the top-level of the design. +However, the true top-level design, the SoC being simulated, is pointed to by the ``TOP`` variable. +This separation allows the infrastructure to separate files based on the harness or the SoC top level. -Common configurations are package using a ``SUB_PROJECT`` make variable. There, in order to simulate a simple Rocket-based example system we can use: +Common configurations of all these variables are packaged using a ``SUB_PROJECT`` make variable. +Therefore, in order to simulate a simple Rocket-based example system we can use: .. code-block:: shell - make SUB_PROJECT=example + make SUB_PROJECT=example Alternatively, if we would like to simulate a simple BOOM-based example system we can use: .. code-block:: shell - make SUB_PROJECT=exampleboom + make SUB_PROJECT=exampleboom - -Once the simulator has been constructed, we would like to run RISC-V programs on it. In the `sims/verisim` directory, we will find an executable file called `TODO`. We run this executable with out target RISC-V program as a command line argument. For example: +Once the simulator has been constructed, we would like to run RISC-V programs on it. +In the simulation directory, we will find an executable file called ``<...>--``. +We run this executable with our target RISC-V program as a command line argument in one of two ways. +One, we can directly call the simulator binary or use make to run the binary for us with extra simulation flags. +For example: .. code-block:: shell - ./simulator-- my_program_binary + # directly calling the simulation binary + ./<...>-- my_program_binary -Alternatively, we can run a pre-packaged suite of RISC-V assembly tests, by adding the make target run-asm-tests. For example + # using make to do it + make SUB_PROJECT=example BINARY=my_program_binary run-binary + +Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. +For example: .. code-block:: shell - make run-asm-tests TOP= CONFIG= SBT_PROJECT= MODEL= - -or - -.. code-block:: shell - - make run-asm-tests SUB_PROJECT=example - - - -VCS -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -VCS is a proprietry RTL simulator. This guide assumes that the VCS installation is found on our PATH. We run VCS simulations from within the ``sims/vsim`` directory. Therefore, we will start by entering the directory: - -.. code-block:: shell - - cd sims/vsim - - -In order to construct the simulator with our custom design, we run the following command within the ``sims/vsim`` directory: - -.. code-block:: shell - - make TOP= CONFIG= SBT_PROJECT= MODEL= - -Where ```` is the class name of the top level design, ```` is the name of the class we create for our parameters configuration, ```` is the name of the sbt package the include both our top-level class and our config class, and ```` is the name of the class which defines the test harness for our system. -The ``make`` command my have additional parameters (such as ``CONFIG_PACKAGE`` or ``MODEL_PACKAGE``) depending on the complexity of the design and integration with multiple sub-project repositories in the sbt-based build system. - -Common configurations are package using a ``SUB_PROJECT`` make variable. There, in order to simulate a simple Rocket-based example system we can use: - -.. code-block:: shell - - make SUB_PROJECT=example - -Alternatively, if we would like to simulate a simple BOOM-based example system we can use: - -.. code-block:: shell - - make SUB_PROJECT=exampleboom - - -Once the simulator has been constructed, we would like to run RISC-V programs on it. In the ``sims/vsim`` directory, we will find an executable file called ``TODO``. We run this executable with out target RISC-V program as a command line argument. For example: - -.. code-block:: shell - - ./simulator-- my_program_binary - -Alternatively, we can run a pre-packaged suite of RISC-V assembly tests, by adding the make target run-asm-tests. For example - -.. code-block:: shell - - make run-asm-tests TOP= CONFIG= SBT_PROJECT= MODEL= - -or - -.. code-block:: shell - - make run-asm-tests SUB_PROJECT=example - + make SUB_PROJECT=example run-asm-tests + make SUB_PROJECT=example run-bmark-tests +Note: You need to specify all the make variables once again to match what the build gave to run the assembly tests or the benchmarks or the binaries if you are using the make option. FPGA Accelerated Simulation --------------------------- -FireSim enables simulations at 1000x-100000x the speed of standard software simulation. This is enabled using FPGA-acceleration on F1 instances of the AWS (Amazon Web Services) public cloud. There FireSim simulation require to be set-up on the AWS public cloud rather than on our local development machine. +FireSim enables simulations at 1000x-100000x the speed of standard software simulation. +This is enabled using FPGA-acceleration on F1 instances of the AWS (Amazon Web Services) public cloud. +Therefore FireSim simulation requires to be set-up on the AWS public cloud rather than on our local development machine. -To run an FPGA-accelerated simulation using FireSim, a we need to clone the ReBAR repository (or our fork of the ReBAR repository) to an AWS EC2, and follow the setup instructions specificied in the FireSim Initial Setup documentation page. +To run an FPGA-accelerated simulation using FireSim, a we need to clone the REBAR repository (or our fork of the REBAR repository) to an AWS EC2, and follow the setup instructions specificied in the FireSim Initial Setup documentation page. -After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design. We will work from within the ``sims/firesim`` directory. +After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design. +We will work from within the ``sims/firesim`` directory. TODO: Continue from here - + diff --git a/docs/Getting-Started/index.rst b/docs/Getting-Started/index.rst index 5976cea6..41eb0392 100644 --- a/docs/Getting-Started/index.rst +++ b/docs/Getting-Started/index.rst @@ -1,9 +1,7 @@ -.. _Getting Started: - Getting Started ================================ -These guides will walk you through the basics of the ReBAR framework: +These guides will walk you through the basics of the REBAR framework: - First, we will go over the different configurations avaliable. @@ -15,8 +13,8 @@ Hit next to get started! :maxdepth: 2 :caption: Getting Started: - ReBAR-Basics - Configs-Parameters-Mixins + REBAR-Basics + Configs-Parameters-Mixins Adding-An-Accelerator-Tutorial Running-A-Simulation rebar-generator-mixins diff --git a/docs/Getting-Started/rebar-generator-mixins.rst b/docs/Getting-Started/rebar-generator-mixins.rst index e950ffda..7599edc3 100644 --- a/docs/Getting-Started/rebar-generator-mixins.rst +++ b/docs/Getting-Started/rebar-generator-mixins.rst @@ -1,5 +1,3 @@ - - SoC Generator Config Mix-ins: ============================== @@ -88,8 +86,8 @@ SiFive Blocks - HasSPIProtocol - HasSPIEndian - HasSPILength - - HasSPICSMode - - HasPeripherySPIFlash + - HasSPICSMode + - HasPeripherySPIFlash - HasPeripheryUART diff --git a/docs/Makefile b/docs/Makefile index 14ce8965..b3492e6c 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -4,7 +4,7 @@ # You can set these variables from the command line. SPHINXOPTS = SPHINXBUILD = python -msphinx -SPHINXPROJ = ReBAR +SPHINXPROJ = REBAR SOURCEDIR = . BUILDDIR = _build @@ -17,4 +17,4 @@ help: # Catch-all target: route all unknown targets to Sphinx using the new # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). %: Makefile - @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) \ No newline at end of file + @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Commercial-Simulators.rst index 27fa5271..1d2f8d35 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/Commercial-Simulators.rst @@ -1,33 +1,37 @@ Commericial Software RTL Simulators ============================== -The ReBAR framework currently supports only the VCS commerical simulator VCS ----------------------- -VCS is a commercial RTL simulator developed by Synopsys. It requires commerical licenses. -The ReBAR framework can compile and execute simulations using VCS. VCS simulation will generally compile -faster than Verilator simulations. + +`VCS `__ is a commercial RTL simulator developed by Synopsys. +It requires commerical licenses. +The REBAR framework can compile and execute simulations using VCS. +VCS simulation will generally compile faster than Verilator simulations. To run a simulation using VCS, perform the following steps: -Make sure that the VCS simulator is on your `PATH`. +Make sure that the VCS simulator is on your ``PATH``. To compile the example design, run make in the ``sims/vsim`` directory. -This will elaborate the DefaultExampleConfig in the example project. +This will elaborate the ``DefaultRocketConfig`` in the example project. -An executable called simulator-example-DefaultExampleConfig will be produced. +An executable called ``simulator-example-DefaultRocketConfig`` will be produced. This executable is a simulator that has been compiled based on the design that was built. -You can then use this executable to run any compatible RV64 code. For instance, -to run one of the riscv-tools assembly tests. +You can then use this executable to run any compatible RV64 code. +For instance, to run one of the riscv-tools assembly tests. -:: - ./simulator-example-DefaultExampleConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple +.. code-block:: shell + ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple -If you later create your own project, you can use environment variables to -build an alternate configuration. +If you later create your own project, you can use environment variables to build an alternate configuration. -:: - make PROJECT=yourproject CONFIG=YourConfig - ./simulator-yourproject-YourConfig ... +.. code-block:: shell + make SUB_PROJECT=yourproject + ./simulator-- ... -If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. This will generate a vpd file (this is a proprietry waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. If you have Synopsys licenses, we recommend using the DVE waveform viewers +If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. +This will generate a vpd file (this is a proprietry waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. +If you have Synopsys licenses, we recommend using the DVE waveform viewer. + +Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running. diff --git a/docs/Simulation/FPGA-Based-Simulators.rst b/docs/Simulation/FPGA-Based-Simulators.rst index 37bc3b16..9ef19d49 100644 --- a/docs/Simulation/FPGA-Based-Simulators.rst +++ b/docs/Simulation/FPGA-Based-Simulators.rst @@ -3,11 +3,15 @@ FPGA-Based Simulators FireSim ----------------------- -FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). -FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. FireSim also provides additional device models to allow full-system simulation, including memory models and network models. -FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. In order to simulate your ReBAR design using FireSim, you should follow the following steps: +`FireSim `__ is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). +FireSim allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators. +FireSim also provides additional device models to allow full-system simulation, including memory models and network models. -Follow the initial EC2 setup instructions as detailed in the `FireSim documentation `__ .. Then clone your full ReBAR repository onto your Amazon EC2 FireSim manager instance. +FireSim currently supports running only on Amazon EC2 F1 FPGA-enabled virtual instances on the public cloud. +In order to simulate your REBAR design using FireSim, you should follow the following steps: + +Follow the initial EC2 setup instructions as detailed in the `FireSim documentation `__. +Then clone your full REBAR repository onto your Amazon EC2 FireSim manager instance. Enter the ``sims/FireSim`` directory, and follow the FireSim instructions for `running a simulation `__. diff --git a/docs/Simulation/Open-Source-Simulators.rst b/docs/Simulation/Open-Source-Simulators.rst index 87edc5ef..53ca3a43 100644 --- a/docs/Simulation/Open-Source-Simulators.rst +++ b/docs/Simulation/Open-Source-Simulators.rst @@ -3,31 +3,31 @@ Open Source Software RTL Simulators Verilator ----------------------- -Verilator is an open-source LGPL-Licensed simulator maintained by `Veripool `__ -The ReBAR framework can download, build, and execute simulations using Verilator. -To run a simulation using verilator, perform the following steps: +`Verilator `__ is an open-source LGPL-Licensed simulator maintained by `Veripool `__. +The REBAR framework can download, build, and execute simulations using Verilator. -To compile the example design, run make in the ``sims/verisim`` directory. -This will elaborate the DefaultExampleConfig in the example project. +To run a simulation using Verilator, perform the following steps: -An executable called simulator-example-DefaultExampleConfig will be produced. +To compile the example design, run ``make`` in the ``sims/verisim`` directory. +This will elaborate the ``DefaultRocketConfig`` in the example project. + +An executable called ``simulator-example-DefaultRocketConfig`` will be produced. This executable is a simulator that has been compiled based on the design that was built. -You can then use this executable to run any compatible RV64 code. For instance, -to run one of the riscv-tools assembly tests. +You can then use this executable to run any compatible RV64 code. +For instance, to run one of the riscv-tools assembly tests. -:: - ./simulator-example-DefaultExampleConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple +.. code-block:: shell + ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple -If you later create your own project, you can use environment variables to -build an alternate configuration. - -:: - make PROJECT=yourproject CONFIG=YourConfig - ./simulator-yourproject-YourConfig ... - - -If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. An open-source vcd-capable waveform viewer is `GTKWave __ +If you later create your own project, you can use environment variables to build an alternate configuration. +.. code-block:: shell + make SUB_PROJECT=yourproject + ./simulator-- ... +If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. +This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. +An open-source vcd-capable waveform viewer is `GTKWave `__. +Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index c5ee90a5..41752cf0 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,8 +1,10 @@ Simulators ======================= -ReBAR provides support and intergration for multiple simulation flows, for various user levels and requirments. -In the majority of cases during a digital design development process, simple software RTL. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. The following pages provide detailed information about the simulation possibilities within the ReBAR framework. +REBAR provides support and intergration for multiple simulation flows, for various user levels and requirments. +In the majority of cases during a digital design development process, a simple software RTL simulation will do. +When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. +The following pages provide detailed information about the simulation possibilities within the REBAR framework. .. toctree:: :maxdepth: 2 diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index 137d95a7..4f8e2ff1 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -1,3 +1,5 @@ Barstools =============================== -Barstools is a collection of useful FIRRTL transformations + +Barstools is a collection of useful FIRRTL transformations and Compilers to help the build process. +Included in the tools are a MacroCompiler (used to map Chisel memory constructs to vendor SRAMs), FIRRTL transforms (to separate harness and top-level SoC files), and more. diff --git a/docs/Tools/Chisel.rst b/docs/Tools/Chisel.rst index 1b0c37ce..3c8293a5 100644 --- a/docs/Tools/Chisel.rst +++ b/docs/Tools/Chisel.rst @@ -1,3 +1,19 @@ Chisel =========================== -TODO: Chisel intro and pointer to chisel bootcamp + +`Chisel `__ is an open-source hardware description language embedded in Scala. +It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM. + +After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog. +First is the compilation step. +If Chisel is thought as a library within Scala, then these classes being built are just Scala classes which call Chisel functions. +Thus, any errors that you get in compiling the Scala/Chisel files are errors that you have violated the typing system, messed up syntax, or more. +After the compilation is complete, elaboration begins. +The Chisel generator starts elaboration using the module and configuration classes passed to it. +This is where the Chisel "library functions" are called with the parameters given and Chisel tries to construct a circuit based on the Chisel code. +If a runtime error happens here, Chisel is stating that it cannot "build" your circuit due to "violations" between your code and the Chisel "library". +However, if that passes, the output of the generator gives you an FIRRTL file and other misc collateral! +See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog. + +For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp `__. +Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <>`__. diff --git a/docs/Tools/FIRRTL.rst b/docs/Tools/FIRRTL.rst index ab5df854..23f39f16 100644 --- a/docs/Tools/FIRRTL.rst +++ b/docs/Tools/FIRRTL.rst @@ -1,3 +1,12 @@ FIRRTL ================================ +`FIRRTL `__ is an intermediate representation of your circuit. +It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog. +Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations. +An example of a FIRRTL pass (transformation) is one that optimizes out unused signals. +Once the transformations are done, a Verilog file is emitted and the build process is done. + +For more information on please visit their `website `__. + + diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index 6b3ad2da..37e0d76e 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -1,7 +1,8 @@ Tools ============================== -The ReBAR framework relays heavily on a set of scala-based tools. While the framework attempts to hide the complexities of these tools, the following pages will introduce them, and how we can use them in order to generate flexible designs +The REBAR framework relays heavily on a set of Scala-based tools. +The following pages will introduce them, and how we can use them in order to generate flexible designs. .. toctree:: :maxdepth: 2 diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst new file mode 100644 index 00000000..a206fe93 --- /dev/null +++ b/docs/VLSI/HAMMER.rst @@ -0,0 +1,7 @@ +HAMMER +================================ + +`HAMMER `__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs. +HAMMER allows for reusability in ASIC design while still providing the designers leeway to make their own modifications. + +For more information, read the `HAMMER paper `__ and see the `GitHub repository `__. diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 5f680b4d..448fadd7 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -1,8 +1,11 @@ VLSI Production ================================ -The ReBAR framework aim to provide wrappers to a general VLSI flow. + +The REBAR framework aim to provide wrappers to a general VLSI flow. In particular, we aim to support the HAMMER flow. .. toctree:: :maxdepth: 2 :caption: VLSI Production: + + HAMMER diff --git a/docs/conf.py b/docs/conf.py index bdddec6c..6afa68ba 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# ReBAR documentation build configuration file, created by +# REBAR documentation build configuration file, created by # sphinx-quickstart on Fri Mar 8 11:46:38 2019. # # This file is execfile()d with the current directory set to its @@ -51,7 +51,7 @@ source_suffix = '.rst' master_doc = 'index' # General information about the project. -project = u'ReBAR' +project = u'REBAR' copyright = u'2019, Berkeley Architecture Research' author = u'Berkeley Architecture Research' @@ -124,7 +124,7 @@ html_sidebars = { # -- Options for HTMLHelp output ------------------------------------------ # Output file base name for HTML help builder. -htmlhelp_basename = 'ReBARdoc' +htmlhelp_basename = 'REBARdoc' # -- Options for LaTeX output --------------------------------------------- @@ -151,7 +151,7 @@ latex_elements = { # (source start file, target name, title, # author, documentclass [howto, manual, or own class]). latex_documents = [ - (master_doc, 'ReBAR.tex', u'ReBAR Documentation', + (master_doc, 'REBAR.tex', u'REBAR Documentation', u'Berkeley Architecture Research', 'manual'), ] @@ -161,7 +161,7 @@ latex_documents = [ # One entry per manual page. List of tuples # (source start file, name, description, authors, manual section). man_pages = [ - (master_doc, 'rebar', u'ReBAR Documentation', + (master_doc, 'rebar', u'REBAR Documentation', [author], 1) ] @@ -172,8 +172,8 @@ man_pages = [ # (source start file, target name, title, author, # dir menu entry, description, category) texinfo_documents = [ - (master_doc, 'ReBAR', u'ReBAR Documentation', - author, 'ReBAR', 'One line description of project.', + (master_doc, 'REBAR', u'REBAR Documentation', + author, 'REBAR', 'One line description of project.', 'Miscellaneous'), ] diff --git a/docs/index.rst b/docs/index.rst index a696f691..73b92ad4 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -1,47 +1,18 @@ -.. ReBAR documentation master file, created by +.. REBAR documentation master file, created by sphinx-quickstart on Fri Mar 8 11:46:38 2019. You can adapt this file completely to your liking, but it should at least contain the root `toctree` directive. -Welcome to ReBAR's documentation! +Welcome to REBAR's documentation! ================================= -ReBAR is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. New to ReBAR? Jump to the :ref:`rebar-basics` page for more info. - - -The documentation outline should look like this - - Getting Started: - - ReBAR-Basics - Initial-Setup/index - Creating-Configuration-Tutorial/index - Adding-An-Accelerator-Tutorial/index - Running-Simulations-Tutorial/index - Building-Chips-Tutorial/index - - Generators: - - Generators/Rocketchip/index - Generators/BOOM/index - Generators/Hwacha/index - - - Simulation: - Simulation/Open-Source-Simulators/index - Simulation/Commercial-Simulators/index - Simulation/FPGA-Based-Simulation/index - - - - Production: - - Production/VLSI-Physical-Design/index - Software/Toolchains/index +REBAR is a a framework for designing and evaluating full-system hardware using agile teams. +It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. +New to REBAR? Jump to the :ref:`Getting Starting` page for more info. .. toctree:: :maxdepth: 3 - :caption: Getting Started: + :caption: Contents: :numbered: Getting-Started/index From 0f34247378185ff1dd83b5c731df4e1b3c76075a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 15:51:25 -0700 Subject: [PATCH 21/36] add section on where to find verilog --- docs/Getting-Started/Running-A-Simulation.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index e67b3813..899d1d41 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -88,6 +88,9 @@ For example: Note: You need to specify all the make variables once again to match what the build gave to run the assembly tests or the benchmarks or the binaries if you are using the make option. +Finally, in the ``generated-src/<...>--/`` directory resides all of the collateral and Verilog source files for the build/simulation. +Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``. + FPGA Accelerated Simulation --------------------------- FireSim enables simulations at 1000x-100000x the speed of standard software simulation. From 3b14ac8706d6a0abe776123e612afb40f7b0558f Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 27 May 2019 17:11:10 -0700 Subject: [PATCH 22/36] minor fixes to links | misc cleanup --- docs/Generators/BOOM.rst | 2 +- .../Adding-An-Accelerator-Tutorial.rst | 20 +++++++++++++++++-- docs/Simulation/Commercial-Simulators.rst | 2 ++ docs/Simulation/Open-Source-Simulators.rst | 2 ++ docs/Tools/Chisel.rst | 2 +- docs/conf.py | 3 ++- docs/index.rst | 2 +- 7 files changed, 27 insertions(+), 6 deletions(-) diff --git a/docs/Generators/BOOM.rst b/docs/Generators/BOOM.rst index e04bed8f..caa7807e 100644 --- a/docs/Generators/BOOM.rst +++ b/docs/Generators/BOOM.rst @@ -8,4 +8,4 @@ Like the R10k and the 21264, BOOM is a unified physical register file design (al Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). -Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages __`. +Additional information about the BOOM micro-architecture can be found in the `BOOM documentation pages `__. diff --git a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst index 6b4c58c5..17d8c51a 100644 --- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst +++ b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst @@ -14,7 +14,8 @@ In contrast, the processor communicates with a RoCC accelerators through a custo Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU. RoCC coprocessor instructions have the following form. -.. code-block:: +.. code-block:: none + customX rd, rs1, rs2, funct The X will be a number 0-3, and determines the opcode of the instruction, which controls which accelerator an instruction will be routed to. @@ -29,7 +30,8 @@ Integrating into the Generator Build System While developing, you want to include Chisel code in a submodule so that it can be shared by different projects. To add a submodule to the REBAR framework, make sure that your project is organized as follows. -.. code-block:: +.. code-block:: none + yourproject/ build.sbt src/main/scala/ @@ -39,12 +41,14 @@ Put this in a git repository and make it accessible. Then add it as a submodule to under the following directory hierarchy: ``generators/yourproject``. .. code-block:: shell + cd generators/ git submodule add https://git-repository.com/yourproject.git Then add ``yourproject`` to the REBAR top-level build.sbt file. .. code-block:: scala + lazy val yourproject = project.settings(commonSettings).dependsOn(rocketchip) You can then import the classes defined in the submodule in a new project if @@ -52,6 +56,7 @@ you add it as a dependency. For instance, if you want to use this code in the ``example`` project, change the final line in build.sbt to the following. .. code-block:: scala + lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) Finally, add ``yourproject`` to the ``PACKAGES`` variable in the ``common.mk`` file in the REBAR top level. @@ -64,6 +69,7 @@ The easiest way to create a TileLink peripheral is to use the ``TLRegisterRouter To create a RegisterRouter-based peripheral, you will need to specify a parameter case class for the configuration settings, a bundle trait with the extra top-level ports, and a module implementation containing the actual RTL. .. code-block:: scala + case class PWMParams(address: BigInt, beatBytes: Int) trait PWMTLBundle extends Bundle { @@ -98,6 +104,7 @@ The second set of arguments is the IO bundle constructor, which we create by ext The final set of arguments is the module constructor, which we create by extends ``TLRegModule`` with our module trait. .. code-block:: scala + class PWMTL(c: PWMParams)(implicit p: Parameters) extends TLRegisterRouter( c.address, "pwm", Seq("ucbbar,pwm"), @@ -116,6 +123,7 @@ The ``LazyModule`` trait runs setup code that must execute before all the hardwa For a simple memory-mapped peripheral, this just involves connecting the peripheral's TileLink node to the MMIO crossbar. .. code-block:: scala + trait HasPeripheryPWM extends HasSystemNetworks { implicit val p: Parameters @@ -138,6 +146,7 @@ Since this module has an extra `pwmout` output, we declare that in this trait, u We then connect the ``PWMTL``'s pwmout to the pwmout we declared. .. code-block:: scala + trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp { implicit val p: Parameters val outer: HasPeripheryPWM @@ -151,6 +160,7 @@ Now we want to mix our traits into the system as a whole. This code is from ``generators/example/src/main/scala/Top.scala``. .. code-block:: scala + class ExampleTopWithPWM(q: Parameters) extends ExampleTop(q) with PeripheryPWM { override lazy val module = Module( @@ -170,6 +180,7 @@ The ``ExampleTopModule`` class is the actual RTL that gets synthesized. Finally, we need to add a configuration class in ``generators/example/src/main/scala/Configs.scala`` that tells the ``TestHarness`` to instantiate ``ExampleTopWithPWM`` instead of the default ``ExampleTop``. .. code-block:: scala + class WithPWM extends Config((site, here, up) => { case BuildTop => (p: Parameters) => Module(LazyModule(new ExampleTopWithPWM()(p)).module) @@ -181,6 +192,7 @@ Finally, we need to add a configuration class in ``generators/example/src/main/s Now we can test that the PWM is working. The test program is in ``tests/pwm.c``. .. code-block:: c + #define PWM_PERIOD 0x2000 #define PWM_DUTY 0x2008 #define PWM_ENABLE 0x2010 @@ -214,6 +226,7 @@ Compiling this program with make produces a ``pwm.riscv`` executable. Now with all of that done, we can go ahead and run our simulation. .. code-block:: shell + cd verisim make CONFIG=PWMConfig ./simulator-example-PWMConfig ../tests/pwm.riscv @@ -225,6 +238,7 @@ RoCC accelerators are lazy modules that extend the ``LazyRoCC`` class. Their implementation should extends the ``LazyRoCCModule`` class. .. code-block:: scala + class CustomAccelerator(opcodes: OpcodeSet) (implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new CustomAcceleratorModule(this) @@ -273,6 +287,7 @@ This takes a sequence of functions producing ``LazyRoCC`` objects, one for each For instance, if we wanted to add the previously defined accelerator and route custom0 and custom1 instructions to it, we could do the following. .. code-block:: scala + class WithCustomAccelerator extends Config((site, here, up) => { case BuildRoCC => Seq((p: Parameters) => LazyModule( new CustomAccelerator(OpcodeSet.custom0 | OpcodeSet.custom1)(p))) @@ -288,6 +303,7 @@ IO devices or accelerators (like a disk or network driver), we may want to have To add a device like that, you would do the following. .. code-block:: scala + class DMADevice(implicit p: Parameters) extends LazyModule { val node = TLClientNode(TLClientParameters( name = "dma-device", sourceId = IdRange(0, 1))) diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Commercial-Simulators.rst index 1d2f8d35..36c3ef3b 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/Commercial-Simulators.rst @@ -22,11 +22,13 @@ You can then use this executable to run any compatible RV64 code. For instance, to run one of the riscv-tools assembly tests. .. code-block:: shell + ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple If you later create your own project, you can use environment variables to build an alternate configuration. .. code-block:: shell + make SUB_PROJECT=yourproject ./simulator-- ... diff --git a/docs/Simulation/Open-Source-Simulators.rst b/docs/Simulation/Open-Source-Simulators.rst index 53ca3a43..11d8d696 100644 --- a/docs/Simulation/Open-Source-Simulators.rst +++ b/docs/Simulation/Open-Source-Simulators.rst @@ -18,11 +18,13 @@ You can then use this executable to run any compatible RV64 code. For instance, to run one of the riscv-tools assembly tests. .. code-block:: shell + ./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple If you later create your own project, you can use environment variables to build an alternate configuration. .. code-block:: shell + make SUB_PROJECT=yourproject ./simulator-- ... diff --git a/docs/Tools/Chisel.rst b/docs/Tools/Chisel.rst index 3c8293a5..947f9666 100644 --- a/docs/Tools/Chisel.rst +++ b/docs/Tools/Chisel.rst @@ -16,4 +16,4 @@ However, if that passes, the output of the generator gives you an FIRRTL file an See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog. For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp `__. -Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <>`__. +Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website `__. diff --git a/docs/conf.py b/docs/conf.py index 6afa68ba..9b7bbe43 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -36,7 +36,8 @@ extensions = ['sphinx.ext.autodoc', 'sphinx.ext.mathjax', 'sphinx.ext.ifconfig', 'sphinx.ext.viewcode', - 'sphinx.ext.githubpages'] + 'sphinx.ext.githubpages', + 'sphinx.ext.autosectionlabel'] # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] diff --git a/docs/index.rst b/docs/index.rst index 73b92ad4..68598e7a 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -8,7 +8,7 @@ Welcome to REBAR's documentation! REBAR is a a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. -New to REBAR? Jump to the :ref:`Getting Starting` page for more info. +New to REBAR? Jump to the :ref:`Getting Started` page for more info. .. toctree:: :maxdepth: 3 From ee62fa8bac1814c41d1d5481ba400d97e908f1c7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 17:21:19 -0700 Subject: [PATCH 23/36] renamed classes to BoomRocket to clarify | clearer comments | readd the bmark timeout --- .../example/src/main/scala/ConfigMixins.scala | 50 ++++++------- .../example/src/main/scala/Configs.scala | 70 +++++++++---------- .../example/src/main/scala/TestHarness.scala | 8 +-- generators/example/src/main/scala/Top.scala | 34 ++++----- variables.mk | 5 +- 5 files changed, 84 insertions(+), 83 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index dbfc1c34..f5e56411 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -42,62 +42,62 @@ class WithGPIO extends Config((site, here, up) => { }) // ----------------------------------------------- -// BOOM + Rocket Top Level System Parameter Mixins +// BOOM and/or Rocket Top Level System Parameter Mixins // ----------------------------------------------- /** - * Class to specify a "plain" top level BOOM + Rocket system + * Class to specify a "plain" top level BOOM and/or Rocket system */ -class WithNormalBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - Module(LazyModule(new BoomAndRocketTop()(p)).module) +class WithNormalBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomRocketTop()(p)).module) } }) /** - * Class to specify a top level BOOM + Rocket system with PWM + * Class to specify a top level BOOM and/or Rocket system with PWM */ -class WithPWMBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomAndRocketTopWithPWMTL()(p)).module) +class WithPWMBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomRocketTopWithPWMTL()(p)).module) }) /** - * Class to specify a top level BOOM + Rocket system with a PWM AXI4 + * Class to specify a top level BOOM and/or Rocket system with a PWM AXI4 */ -class WithPWMAXI4BoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => - Module(LazyModule(new BoomAndRocketTopWithPWMAXI4()(p)).module) +class WithPWMAXI4BoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomRocketTopWithPWMAXI4()(p)).module) }) /** - * Class to specify a top level BOOM + Rocket system with a block device + * Class to specify a top level BOOM and/or Rocket system with a block device */ -class WithBlockDeviceModelBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) +class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module) top.connectBlockDeviceModel() top } }) /** - * Class to specify a top level BOOM + Rocket system with a simulator block device + * Class to specify a top level BOOM and/or Rocket system with a simulator block device */ -class WithSimBlockDeviceBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) +class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module) top.connectSimBlockDevice(clock, reset) top } }) /** - * Class to specify a top level BOOM + Rocket system with GPIO + * Class to specify a top level BOOM and/or Rocket system with GPIO */ -class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { - case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { - val top = Module(LazyModule(new BoomAndRocketTopWithGPIO()(p)).module) +class WithGPIOBoomRocketTop extends Config((site, here, up) => { + case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomRocketTopWithGPIO()(p)).module) for (gpio <- top.gpio) { for (pin <- gpio.pins) { pin.i.ival := false.B diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 98a37bc7..114d8baa 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -16,7 +16,7 @@ class BaseRocketConfig extends Config( new freechips.rocketchip.system.DefaultConfig) class DefaultRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new BaseRocketConfig) class HwachaConfig extends Config( @@ -28,26 +28,26 @@ class RoccRocketConfig extends Config( new DefaultRocketConfig) class PWMRocketConfig extends Config( - new WithPWMBoomAndRocketTop ++ + new WithPWMBoomRocketTop ++ new BaseRocketConfig) class PWMAXI4RocketConfig extends Config( - new WithPWMAXI4BoomAndRocketTop ++ + new WithPWMAXI4BoomRocketTop ++ new BaseRocketConfig) class SimBlockDeviceRocketConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomAndRocketTop ++ + new WithSimBlockDeviceBoomRocketTop ++ new BaseRocketConfig) class BlockDeviceModelRocketConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomAndRocketTop ++ + new WithBlockDeviceModelBoomRocketTop ++ new BaseRocketConfig) class GPIORocketConfig extends Config( new WithGPIO ++ - new WithGPIOBoomAndRocketTop ++ + new WithGPIOBoomRocketTop ++ new BaseRocketConfig) class DualCoreRocketConfig extends Config( @@ -75,11 +75,11 @@ class SmallBaseBoomConfig extends Config( new boom.system.SmallBoomConfig) class DefaultBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new BaseBoomConfig) class SmallDefaultBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new SmallBaseBoomConfig) class HwachaBoomConfig extends Config( @@ -91,26 +91,26 @@ class RoccBoomConfig extends Config( new DefaultBoomConfig) class PWMBoomConfig extends Config( - new WithPWMBoomAndRocketTop ++ + new WithPWMBoomRocketTop ++ new BaseBoomConfig) class PWMAXI4BoomConfig extends Config( - new WithPWMAXI4BoomAndRocketTop ++ + new WithPWMAXI4BoomRocketTop ++ new BaseBoomConfig) class SimBlockDeviceBoomConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomAndRocketTop ++ + new WithSimBlockDeviceBoomRocketTop ++ new BaseBoomConfig) class BlockDeviceModelBoomConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomAndRocketTop ++ + new WithBlockDeviceModelBoomRocketTop ++ new BaseBoomConfig) class GPIOBoomConfig extends Config( new WithGPIO ++ - new WithGPIOBoomAndRocketTop ++ + new WithGPIOBoomRocketTop ++ new BaseBoomConfig) /** @@ -118,7 +118,7 @@ class GPIOBoomConfig extends Config( * the `WithNBoomCores` with the DefaultBoomConfig params */ class DualCoreBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.DefaultBoomConfig ++ @@ -127,7 +127,7 @@ class DualCoreBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreSmallBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.common.WithRVC ++ new boom.common.WithSmallBooms ++ @@ -137,12 +137,12 @@ class DualCoreSmallBoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class RV32UnifiedBoomConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.SmallRV32UnifiedBoomConfig) // --------------------- -// BOOM + Rocket Configs +// BOOM and Rocket Configs // --------------------- class BaseBoomAndRocketConfig extends Config( @@ -167,46 +167,46 @@ class SmallBaseBoomAndRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DefaultBoomAndRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithNormalBoomRocketTop ++ + new BaseBoomRocketConfig) class SmallDefaultBoomAndRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ - new SmallBaseBoomAndRocketConfig) + new WithNormalBoomRocketTop ++ + new SmallBaseBoomRocketConfig) class HwachaBoomAndRocketConfig extends Config( new hwacha.DefaultHwachaConfig ++ - new DefaultBoomAndRocketConfig) + new DefaultBoomRocketConfig) class RoccBoomAndRocketConfig extends Config( new WithRoccExample ++ - new DefaultBoomAndRocketConfig) + new DefaultBoomRocketConfig) class PWMBoomAndRocketConfig extends Config( - new WithPWMBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithPWMBoomRocketTop ++ + new BaseBoomRocketConfig) class PWMAXI4BoomAndRocketConfig extends Config( - new WithPWMAXI4BoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithPWMAXI4BoomRocketTop ++ + new BaseBoomRocketConfig) class SimBlockDeviceBoomAndRocketConfig extends Config( new WithBlockDevice ++ - new WithSimBlockDeviceBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithSimBlockDeviceBoomRocketTop ++ + new BaseBoomRocketConfig) class BlockDeviceModelBoomAndRocketConfig extends Config( new WithBlockDevice ++ - new WithBlockDeviceModelBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithBlockDeviceModelBoomRocketTop ++ + new BaseBoomRocketConfig) class GPIOBoomAndRocketConfig extends Config( new WithGPIO ++ - new WithGPIOBoomAndRocketTop ++ - new BaseBoomAndRocketConfig) + new WithGPIOBoomRocketTop ++ + new BaseBoomRocketConfig) class DualCoreBoomAndOneRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.WithRenumberHarts ++ new boom.common.WithRVC ++ @@ -217,7 +217,7 @@ class DualCoreBoomAndOneRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) class RV32BoomAndRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new boom.system.WithRenumberHarts ++ new boom.common.WithBoomRV32 ++ diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index 7bad5cbc..c59a081e 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -10,12 +10,12 @@ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp // -------------------------- -// BOOM + Rocket Test Harness +// BOOM and/or Rocket Test Harness // -------------------------- -case object BuildBoomAndRocketTop extends Field[(Clock, Bool, Parameters) => BoomAndRocketTopModule[BoomAndRocketTop]] +case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]] -class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module { +class BoomRocketTestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) @@ -23,7 +23,7 @@ class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module { // force Chisel to rename module override def desiredName = "TestHarness" - val dut = p(BuildBoomAndRocketTop)(clock, reset.toBool, p) + val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p) dut.debug := DontCare dut.connectSimAXIMem() dut.connectSimAXIMMIO() diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index ddd4a20f..5ee73906 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -13,57 +13,57 @@ import testchipip._ import sifive.blocks.devices.gpio._ // ------------------------------- -// BOOM + Rocket Top Level Systems +// BOOM and/or Rocket Top Level Systems // ------------------------------- -class BoomAndRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem +class BoomRocketTop(implicit p: Parameters) extends boom.system.ExampleBoomAndRocketSystem with HasNoDebug with HasPeripherySerial { - override lazy val module = new BoomAndRocketTopModule(this) + override lazy val module = new BoomRocketTopModule(this) } -class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) +class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.ExampleBoomAndRocketSystemModule(l) with HasNoDebugModuleImp with HasPeripherySerialModuleImp with DontTouch //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithPWMTL(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithPWMTL(implicit p: Parameters) extends BoomRocketTop with HasPeripheryPWMTL { - override lazy val module = new BoomAndRocketTopWithPWMTLModule(this) + override lazy val module = new BoomRocketTopWithPWMTLModule(this) } -class BoomAndRocketTopWithPWMTLModule(l: BoomAndRocketTopWithPWMTL) extends BoomAndRocketTopModule(l) +class BoomRocketTopWithPWMTLModule(l: BoomRocketTopWithPWMTL) extends BoomRocketTopModule(l) with HasPeripheryPWMTLModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomRocketTop with HasPeripheryPWMAXI4 { - override lazy val module = new BoomAndRocketTopWithPWMAXI4Module(this) + override lazy val module = new BoomRocketTopWithPWMAXI4Module(this) } -class BoomAndRocketTopWithPWMAXI4Module(l: BoomAndRocketTopWithPWMAXI4) extends BoomAndRocketTopModule(l) +class BoomRocketTopWithPWMAXI4Module(l: BoomRocketTopWithPWMAXI4) extends BoomRocketTopModule(l) with HasPeripheryPWMAXI4ModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithBlockDevice(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithBlockDevice(implicit p: Parameters) extends BoomRocketTop with HasPeripheryBlockDevice { - override lazy val module = new BoomAndRocketTopWithBlockDeviceModule(this) + override lazy val module = new BoomRocketTopWithBlockDeviceModule(this) } -class BoomAndRocketTopWithBlockDeviceModule(l: BoomAndRocketTopWithBlockDevice) extends BoomAndRocketTopModule(l) +class BoomRocketTopWithBlockDeviceModule(l: BoomRocketTopWithBlockDevice) extends BoomRocketTopModule(l) with HasPeripheryBlockDeviceModuleImp //--------------------------------------------------------------------------------------------------------- -class BoomAndRocketTopWithGPIO(implicit p: Parameters) extends BoomAndRocketTop +class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop with HasPeripheryGPIO { - override lazy val module = new BoomAndRocketTopWithGPIOModule(this) + override lazy val module = new BoomRocketTopWithGPIOModule(this) } -class BoomAndRocketTopWithGPIOModule(l: BoomAndRocketTopWithGPIO) - extends BoomAndRocketTopModule(l) +class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO) + extends BoomRocketTopModule(l) with HasPeripheryGPIOModuleImp diff --git a/variables.mk b/variables.mk index f73d7f7a..7545e9a3 100644 --- a/variables.mk +++ b/variables.mk @@ -29,14 +29,14 @@ SUB_PROJECT ?= example ifeq ($(SUB_PROJECT),example) SBT_PROJECT ?= example - MODEL ?= BoomAndRocketTestHarness + MODEL ?= BoomRocketTestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) CONFIG ?= DefaultRocketConfig CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= BoomAndRocketTop + TOP ?= BoomRocketTop endif # for BOOM developers ifeq ($(SUB_PROJECT),boom) @@ -162,3 +162,4 @@ sim_vsrcs = \ # assembly/benchmark variables ######################################################################################### timeout_cycles = 10000000 +bmark_timeout_cycles = 100000000 From d51ab9cde6d47c79cf7ceb9e9098524404dca58b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 17:26:44 -0700 Subject: [PATCH 24/36] only change default SIM_FLAGS | revert .run and .out flags --- common.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index 3d67cebd..f7e46608 100644 --- a/common.mk +++ b/common.mk @@ -86,10 +86,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< && touch $@ + $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< && touch $@ $(output_dir)/%.out: $(output_dir)/% $(sim) - $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ + $(sim) $(PERMISSIVE_ON) +verbose +max-cycles=$(timeout_cycles) $(PERMISSIVE_OFF) $< 3>&1 1>&2 2>&3 | spike-dasm > $@ ######################################################################################### # include build/project specific makefrags made from the generator From c160f597b78858ef995900d07f784ca7d09edbc2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 19:07:55 -0700 Subject: [PATCH 25/36] spelling check | better heading for accelerators --- docs/Generators/BOOM.rst | 2 +- docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst | 4 ++-- docs/Getting-Started/Development-Ecosystem.rst | 2 +- docs/Getting-Started/REBAR-Basics.rst | 2 +- docs/Getting-Started/Running-A-Simulation.rst | 2 +- docs/Getting-Started/index.rst | 2 +- docs/Simulation/Commercial-Simulators.rst | 6 +++--- docs/Simulation/index.rst | 2 +- 8 files changed, 11 insertions(+), 11 deletions(-) diff --git a/docs/Generators/BOOM.rst b/docs/Generators/BOOM.rst index caa7807e..6dcdb41f 100644 --- a/docs/Generators/BOOM.rst +++ b/docs/Generators/BOOM.rst @@ -3,7 +3,7 @@ Berkeley Out-of-Order Machine (BOOM) The `Berkeley Out-of-Order Machine (BOOM) `__ is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. It serves as a drop-in replacement to the Rocket core given by Rocket Chip. -BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 outoforder processors. +BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 out-of-order processors. Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”). Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit. However, many of those stages are combined in the current implementation, yielding seven stages: Fetch, Decode/Rename, Rename/Dispatch, Issue/RegisterRead, Execute, Memory and Writeback (Commit occurs asynchronously, so it is not counted as part of the “pipeline”). diff --git a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst index 17d8c51a..bad5ceef 100644 --- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst +++ b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst @@ -22,7 +22,7 @@ The X will be a number 0-3, and determines the opcode of the instruction, which The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination register and two source registers. The ``funct`` field is a 7-bit integer that the accelerator can use to distinguish different instructions from each other. -Note that communication through a RoCC interface requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with approriate driver support. +Note that communication through a RoCC interface requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with appropriate driver support. Integrating into the Generator Build System ------------------------------------------- @@ -138,7 +138,7 @@ For a simple memory-mapped peripheral, this just involves connecting the periphe Note that the ``PWMTL`` class we created from the register router is itself a ``LazyModule``. -Register routers have a TileLike node simply named "node", which we can hook up to the Rocket Chip bus. +Register routers have a TileLink node simply named "node", which we can hook up to the Rocket Chip bus. This will automatically add address map and device tree entries for the peripheral. The module implementation trait is where we instantiate our PWM module and connect it to the rest of the SoC. diff --git a/docs/Getting-Started/Development-Ecosystem.rst b/docs/Getting-Started/Development-Ecosystem.rst index 8946a319..fa407194 100644 --- a/docs/Getting-Started/Development-Ecosystem.rst +++ b/docs/Getting-Started/Development-Ecosystem.rst @@ -13,7 +13,7 @@ Chisel/FIRRTL One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language `__ and the `FIRRTL Compiler `__. Chisel is an embedded language within Scala that provides a set of libraries to help hardware designers create highly parameterizable RTL. -FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimation, circuit analysis, connectivity checks, and much more! +FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more! These two tools in combination allow quick design space exploration and development of new RTL. Generators diff --git a/docs/Getting-Started/REBAR-Basics.rst b/docs/Getting-Started/REBAR-Basics.rst index 69963b3e..5dcac5d7 100644 --- a/docs/Getting-Started/REBAR-Basics.rst +++ b/docs/Getting-Started/REBAR-Basics.rst @@ -17,7 +17,7 @@ Processor Cores An out-of-order RISC-V core. See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. -Data-Parallel Accelerators +Accelerators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ **Hwacha** diff --git a/docs/Getting-Started/Running-A-Simulation.rst b/docs/Getting-Started/Running-A-Simulation.rst index 899d1d41..673bf0ae 100644 --- a/docs/Getting-Started/Running-A-Simulation.rst +++ b/docs/Getting-Started/Running-A-Simulation.rst @@ -97,7 +97,7 @@ FireSim enables simulations at 1000x-100000x the speed of standard software simu This is enabled using FPGA-acceleration on F1 instances of the AWS (Amazon Web Services) public cloud. Therefore FireSim simulation requires to be set-up on the AWS public cloud rather than on our local development machine. -To run an FPGA-accelerated simulation using FireSim, a we need to clone the REBAR repository (or our fork of the REBAR repository) to an AWS EC2, and follow the setup instructions specificied in the FireSim Initial Setup documentation page. +To run an FPGA-accelerated simulation using FireSim, a we need to clone the REBAR repository (or our fork of the REBAR repository) to an AWS EC2, and follow the setup instructions specified in the FireSim Initial Setup documentation page. After setting up the FireSim environment, we now need to generate a FireSim simulation around our selected digital design. We will work from within the ``sims/firesim`` directory. diff --git a/docs/Getting-Started/index.rst b/docs/Getting-Started/index.rst index 41eb0392..61a77dec 100644 --- a/docs/Getting-Started/index.rst +++ b/docs/Getting-Started/index.rst @@ -3,7 +3,7 @@ Getting Started These guides will walk you through the basics of the REBAR framework: -- First, we will go over the different configurations avaliable. +- First, we will go over the different configurations available. - Then, we will walk through adding a custom accelerator. diff --git a/docs/Simulation/Commercial-Simulators.rst b/docs/Simulation/Commercial-Simulators.rst index 36c3ef3b..8c1c34d7 100644 --- a/docs/Simulation/Commercial-Simulators.rst +++ b/docs/Simulation/Commercial-Simulators.rst @@ -1,11 +1,11 @@ -Commericial Software RTL Simulators +Commercial Software RTL Simulators ============================== VCS ----------------------- `VCS `__ is a commercial RTL simulator developed by Synopsys. -It requires commerical licenses. +It requires commercial licenses. The REBAR framework can compile and execute simulations using VCS. VCS simulation will generally compile faster than Verilator simulations. @@ -33,7 +33,7 @@ If you later create your own project, you can use environment variables to build ./simulator-- ... If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. -This will generate a vpd file (this is a proprietry waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. +This will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. If you have Synopsys licenses, we recommend using the DVE waveform viewer. Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index 41752cf0..d61b5ed7 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,7 +1,7 @@ Simulators ======================= -REBAR provides support and intergration for multiple simulation flows, for various user levels and requirments. +REBAR provides support and integration for multiple simulation flows, for various user levels and requirements. In the majority of cases during a digital design development process, a simple software RTL simulation will do. When more advanced full-system evaluation is required, with long running workloads, FPGA-accelerated simulation will then become a preferable solution. The following pages provide detailed information about the simulation possibilities within the REBAR framework. From 540afea07aef44b7e8b2614c397659ba66908232 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 27 May 2019 19:12:07 -0700 Subject: [PATCH 26/36] fix config naming --- .../example/src/main/scala/Configs.scala | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 114d8baa..edf1be75 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -168,42 +168,42 @@ class SmallBaseBoomAndRocketConfig extends Config( class DefaultBoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class SmallDefaultBoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ - new SmallBaseBoomRocketConfig) + new SmallBaseBoomAndRocketConfig) class HwachaBoomAndRocketConfig extends Config( new hwacha.DefaultHwachaConfig ++ - new DefaultBoomRocketConfig) + new DefaultBoomAndRocketConfig) class RoccBoomAndRocketConfig extends Config( new WithRoccExample ++ - new DefaultBoomRocketConfig) + new DefaultBoomAndRocketConfig) class PWMBoomAndRocketConfig extends Config( new WithPWMBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class PWMAXI4BoomAndRocketConfig extends Config( new WithPWMAXI4BoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class SimBlockDeviceBoomAndRocketConfig extends Config( new WithBlockDevice ++ new WithSimBlockDeviceBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class BlockDeviceModelBoomAndRocketConfig extends Config( new WithBlockDevice ++ new WithBlockDeviceModelBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class GPIOBoomAndRocketConfig extends Config( new WithGPIO ++ new WithGPIOBoomRocketTop ++ - new BaseBoomRocketConfig) + new BaseBoomAndRocketConfig) class DualCoreBoomAndOneRocketConfig extends Config( new WithNormalBoomRocketTop ++ From 7e6591b5ea1aff4ac77fbf6d3236fc56a55a134e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 17:58:12 -0700 Subject: [PATCH 27/36] add multi-rocc and show small example --- .../example/src/main/scala/ConfigMixins.scala | 40 +++++++++++++++++++ .../example/src/main/scala/Configs.scala | 14 +++++++ 2 files changed, 54 insertions(+) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index f5e56411..0c304d60 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -106,3 +106,43 @@ class WithGPIOBoomRocketTop extends Config((site, here, up) => { top } }) + +// ------------------ +// Multi-RoCC Support +// ------------------ + +/** + * Map from a hartId to a particular RoCC accelerator + */ +case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]]) + +/** + * Mixin to enable different RoCCs based on the hartId + */ +class WithMultiRoCC extends Config((site, here, up) => { + case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil) +}) + +/** + * Mixin to add Hwachas to cores based on hart + * + * For ex: + * Core 0, 1, 2, 3 have been defined earlier + * with hartIds of 0, 1, 2, 3 respectively + * And you call WithMultiRoCCHwacha(Seq(0,1)) + * Then Core 0 and 1 will get a Hwacha + * + * @param harts Seq of harts to specifiy which will get a Hwacha + */ +class WithMultiRoCCHwacha(harts: Seq[Int]) extends Config((site, here, up) => { + case MultiRoCCKey => { + require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1)) + up(MultiRoCCKey, site) ++ harts.distinct.map{ i => + (i -> Seq((p: Parameters) => { + implicit val q = p + implicit val v = implicitly[ValName] + LazyModule(new Hwacha()(p)) + })) + } + } +}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index edf1be75..9338f4e7 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -216,6 +216,20 @@ class DualCoreBoomAndOneRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) +class DualCoreBoomAndOneHwachaRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new WithBootROM ++ + new WithMultiRoCC ++ + new WithMultiRoCCHwacha(Seq(0)) ++ // put Hwacha just on hart0 which was renumbered to Rocket + new boom.system.WithRenumberHarts ++ + new hwacha.DefaultHwachaConfig ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + class RV32BoomAndRocketConfig extends Config( new WithNormalBoomRocketTop ++ new WithBootROM ++ From 41b4637c293eafa1021d4145b011d52bc7087b79 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 24 May 2019 21:13:14 -0700 Subject: [PATCH 28/36] build and name hwacha correctly --- generators/boom | 2 +- .../example/src/main/scala/ConfigMixins.scala | 16 +++++++++------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/generators/boom b/generators/boom index 92313af2..2f8c419f 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 92313af2a0ed4d8a93591a08f42ede1a0ffd808a +Subproject commit 2f8c419ff8fa7d848d0d92d4977885cb1e1fa5b3 diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 0c304d60..69e2b08b 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -3,14 +3,18 @@ package example import chisel3._ import chisel3.util.{log2Up} -import freechips.rocketchip.config.{Parameters, Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} +import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.subsystem.{RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32} import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.devices.tilelink.BootROMParams -import freechips.rocketchip.tile.{XLen} +import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC} + +import boom.system.{BoomTilesKey} import testchipip._ +import hwacha.{Hwacha} + import sifive.blocks.devices.gpio._ /** @@ -132,16 +136,14 @@ class WithMultiRoCC extends Config((site, here, up) => { * And you call WithMultiRoCCHwacha(Seq(0,1)) * Then Core 0 and 1 will get a Hwacha * - * @param harts Seq of harts to specifiy which will get a Hwacha + * @param harts Seq of harts to specify which will get a Hwacha */ class WithMultiRoCCHwacha(harts: Seq[Int]) extends Config((site, here, up) => { case MultiRoCCKey => { require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1)) up(MultiRoCCKey, site) ++ harts.distinct.map{ i => (i -> Seq((p: Parameters) => { - implicit val q = p - implicit val v = implicitly[ValName] - LazyModule(new Hwacha()(p)) + LazyModule(new Hwacha()(p)).suggestName("hwacha") })) } } From 4ad54ced98326078ace1bb5cfdeb6be136659e56 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sun, 26 May 2019 17:44:27 -0700 Subject: [PATCH 29/36] use varargs instead of seq --- generators/example/src/main/scala/ConfigMixins.scala | 6 +++--- generators/example/src/main/scala/Configs.scala | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 69e2b08b..895fa86a 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -133,12 +133,12 @@ class WithMultiRoCC extends Config((site, here, up) => { * For ex: * Core 0, 1, 2, 3 have been defined earlier * with hartIds of 0, 1, 2, 3 respectively - * And you call WithMultiRoCCHwacha(Seq(0,1)) + * And you call WithMultiRoCCHwacha(0,1) * Then Core 0 and 1 will get a Hwacha * - * @param harts Seq of harts to specify which will get a Hwacha + * @param harts harts to specify which will get a Hwacha */ -class WithMultiRoCCHwacha(harts: Seq[Int]) extends Config((site, here, up) => { +class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { case MultiRoCCKey => { require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1)) up(MultiRoCCKey, site) ++ harts.distinct.map{ i => diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 9338f4e7..cba65d32 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -220,7 +220,7 @@ class DualCoreBoomAndOneHwachaRocketConfig extends Config( new WithNormalBoomAndRocketTop ++ new WithBootROM ++ new WithMultiRoCC ++ - new WithMultiRoCCHwacha(Seq(0)) ++ // put Hwacha just on hart0 which was renumbered to Rocket + new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket new boom.system.WithRenumberHarts ++ new hwacha.DefaultHwachaConfig ++ new boom.common.WithRVC ++ From fa080b7857d3b1fff5639a2d87fb5f9a60321a2a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 28 May 2019 12:46:57 -0700 Subject: [PATCH 30/36] fix top level naming --- generators/example/src/main/scala/Configs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index cba65d32..d6ff3432 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -217,7 +217,7 @@ class DualCoreBoomAndOneRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreBoomAndOneHwachaRocketConfig extends Config( - new WithNormalBoomAndRocketTop ++ + new WithNormalBoomRocketTop ++ new WithBootROM ++ new WithMultiRoCC ++ new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket From a4010bc5127c77138de5ffe0dc3fb6f6dc7df0f5 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 28 May 2019 16:08:35 -0700 Subject: [PATCH 31/36] Update README (mainly just have links to the documentation) --- README.md | 462 +++--------------------------------------------------- 1 file changed, 20 insertions(+), 442 deletions(-) diff --git a/README.md b/README.md index a4ef1c81..559431f2 100644 --- a/README.md +++ b/README.md @@ -1,449 +1,27 @@ -# RISC-V Project Template [![CircleCI](https://circleci.com/gh/ucb-bar/project-template/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/project-template/tree/master) +# REBAR Framework [![CircleCI](https://circleci.com/gh/ucb-bar/project-template/tree/master.svg?style=svg)](https://circleci.com/gh/ucb-bar/project-template/tree/master) -**This branch is under development** -**It currently has many submodules** -**Please run ./scripts/init-submodules-no-riscv-tools.sh to update submodules, unless you want to spend a long time waiting for submodules to clone** +## Using REBAR -This is a starter template for your custom RISC-V project. It will allow you -to leverage the Chisel HDL and RocketChip SoC generator to produce a -RISC-V SoC with MMIO-mapped peripherals, DMA, and custom accelerators. +To get started using REBAR, see the documentation on the REBAR documentation site: https://bar-project-template.readthedocs.io/en/latest/ -## Getting started +## What is REBAR -### Checking out the sources +REBAR is an open source starter template for your custom Chisel project. +It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. +It contains processor cores ([Rocket][rocket], [BOOM][boom]), accelerators ([Hwacha][hwacha]), FPGA simulation tools ([FireSim][firesim]), ASIC tools ([HAMMER][hammer]) and other tooling to help create a full featured SoC. +REBAR is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. -After cloning this repo, you will need to initialize all of the submodules +## Resources - git clone https://github.com/ucb-bar/project-template.git - cd project-template - git submodule update --init --recursive +* REBAR Website: ...TBD at a later date... +* REBAR Documentation: https://bar-project-template.readthedocs.io/ -### Building the tools - -The tools repo contains the cross-compiler toolchain, frontend server, and -proxy kernel, which you will need in order to compile code to RISC-V -instructions and run them on your design. There are detailed instructions at -https://github.com/riscv/riscv-tools. But to get a basic installation, just -the following steps are necessary. - - # You may want to add the following two lines to your shell profile - export RISCV=/path/to/install/dir - export PATH=$RISCV/bin:$PATH - - cd rocket-chip/riscv-tools - ./build.sh - -### Compiling and running the Verilator simulation - -To compile the example design, run make in the "verisim" directory. -This will elaborate the DefaultExampleConfig in the example project. - -An executable called simulator-example-DefaultExampleConfig will be produced. -You can then use this executable to run any compatible RV64 code. For instance, -to run one of the riscv-tools assembly tests. - - ./simulator-example-DefaultExampleConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple - -If you later create your own project, you can use environment variables to -build an alternate configuration. - - make PROJECT=yourproject CONFIG=YourConfig - ./simulator-yourproject-YourConfig ... - -Additionally, you can use a helper make rule to run your simulation binary. The output will be in the "verisim" -directory under the file names: `..*` - - # first make your verisim rtl simulator binary - make SUB_PROJECT=example - # then run the binary (with no vcd generation) - make SUB_PROJECT=example BINARY= run-binary - # then run the binary (with vcd generation) - make SUB_PROJECT=example BINARY= run-binary-debug - -## Submodules and Subdirectories - -The submodules and subdirectories for the project template are organized as -follows. - - * rocket-chip - contains code for the RocketChip generator and Chisel HDL - * testchipip - contains the serial adapter, block device, and associated verilog and C++ code - * verisim - directory in which Verilator simulations are compiled and run - * vsim - directory in which Synopsys VCS simulations are compiled and run - * bootrom - sources for the first-stage bootloader included in the Boot ROM - * src/main/scala - scala source files for your project go here - -## For submodule developers - -Depending on the submodule that you develop in, you might want to run things out of the submodule. -For example, `boom` has its own Generator, package, top module, and configurations separate from -the `example` package in `src/main/scala`. Thus, to build a `boom` project you do something like -the following: - - make SBT_PROJECT=boom PROJECT=boom.system CONFIG= TOP=ExampleBoomSystem - -However, that is very long to write everytime there is a compile. Thus, a shorthand way to build -the subproject is the following: - - make SUB_PROJECT=boom CONFIG= - -This sets the proper configuration flags for make to work correctly. - -Currently, the supported `SUB_PROJECT` flags are: - - * boom - to build and run `boom` subproject configurations - -## Using the block device - -The default example project just provides the Rocket coreplex, memory, and -serial line. But testchipip also provides a simulated block device that can -be used for non-volatile storage. You can build a simulator including the -block device using the blkdev package. - - make CONFIG=SimBlockDeviceConfig - ./simulator-example-SimBlockDeviceConfig +blkdev=block-device.img ... - -By passing the +blkdev argument on the simulator command line, you can allow -the RTL simulation to read and write from a file. Take a look at tests/blkdev.c -for an example of how Rocket can program the block device controller. - -## Adding an MMIO peripheral - -You can RocketChip to create your own memory-mapped IO device and add it into -the SoC design. The easiest way to create a TileLink peripheral is to use the -TLRegisterRouter, which abstracts away the details of handling the TileLink -protocol and provides a convenient interface for specifying memory-mapped -registers. To create a RegisterRouter-based peripheral, you will need to -specify a parameter case class for the configuration settings, a bundle trait -with the extra top-level ports, and a module implementation containing the -actual RTL. - -```scala - case class PWMParams(address: BigInt, beatBytes: Int) - - trait PWMTLBundle extends Bundle { - val pwmout = Output(Bool()) - } - - trait PWMTLModule { - val io: PWMTLBundle - implicit val p: Parameters - def params: PWMParams - - val w = params.beatBytes * 8 - val period = Reg(UInt(w.W)) - val duty = Reg(UInt(w.W)) - val enable = RegInit(false.B) - - // ... Use the registers to drive io.pwmout ... - - regmap( - 0x00 -> Seq( - RegField(w, period)), - 0x04 -> Seq( - RegField(w, duty)), - 0x08 -> Seq( - RegField(1, enable))) - } -``` - -Once you have these classes, you can construct the final peripheral by -extending the TLRegisterRouter and passing the proper arguments. The first -set of arguments determines where the register router will be placed in the -global address map and what information will be put in its device tree entry. -The second set of arguments is the IO bundle constructor, which we create -by extending TLRegBundle with our bundle trait. The final set of arguments -is the module constructor, which we create by extends TLRegModule with our -module trait. - -```scala - class PWMTL(c: PWMParams)(implicit p: Parameters) - extends TLRegisterRouter( - c.address, "pwm", Seq("ucbbar,pwm"), - beatBytes = c.beatBytes)( - new TLRegBundle(c, _) with PWMTLBundle)( - new TLRegModule(c, _, _) with PWMTLModule) -``` - -The full module code with comments can be found in src/main/scala/example/PWM.scala. - -After creating the module, we need to hook it up to our SoC. Rocketchip -accomplishes this using the [cake pattern](http://www.cakesolutions.net/teamblogs/2011/12/19/cake-pattern-in-depth). -This basically involves placing code inside traits. In the RocketChip cake, -there are two kinds of traits: a LazyModule trait and a module implementation -trait. - -The LazyModule trait runs setup code that must execute before all the hardware -gets elaborated. For a simple memory-mapped peripheral, this just involves -connecting the peripheral's TileLink node to the MMIO crossbar. - -```scala - trait HasPeripheryPWM extends HasSystemNetworks { - implicit val p: Parameters - - private val address = 0x2000 - - val pwm = LazyModule(new PWMTL( - PWMParams(address, peripheryBusConfig.beatBytes))(p)) - - pwm.node := TLFragmenter( - peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) - } -``` - -Note that the PWMTL class we created from the register router is itself a -LazyModule. Register routers have a TileLike node simply named "node", which -we can hook up to the RocketChip peripheryBus. This will automatically add -address map and device tree entries for the peripheral. - -The module implementation trait is where we instantiate our PWM module and -connect it to the rest of the SoC. Since this module has an extra `pwmout` -output, we declare that in this trait, using Chisel's multi-IO -functionality. We then connect the PWMTL's pwmout to the pwmout we declared. - -```scala - trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp { - implicit val p: Parameters - val outer: HasPeripheryPWM - - val pwmout = IO(Output(Bool())) - - pwmout := outer.pwm.module.io.pwmout - } -``` - -Now we want to mix our traits into the system as a whole. This code is from -src/main/scala/example/Top.scala. - -```scala - class ExampleTopWithPWM(q: Parameters) extends ExampleTop(q) - with PeripheryPWM { - override lazy val module = Module( - new ExampleTopWithPWMModule(p, this)) - } - - class ExampleTopWithPWMModule(l: ExampleTopWithPWM) - extends ExampleTopModule(l) with HasPeripheryPWMModuleImp -``` - -Just as we need separate traits for LazyModule and module implementation, we -need two classes to build the system. The ExampleTop classes already have the -basic peripherals included for us, so we will just extend those. - -The ExampleTop class includes the pre-elaboration code and also a lazy val to -produce the module implementation (hence LazyModule). The ExampleTopModule -class is the actual RTL that gets synthesized. - -Finally, we need to add a configuration class in -src/main/scala/example/Configs.scala that tells the TestHarness to instantiate -ExampleTopWithPWM instead of the default ExampleTop. - -```scala - class WithPWM extends Config((site, here, up) => { - case BuildTop => (p: Parameters) => - Module(LazyModule(new ExampleTopWithPWM()(p)).module) - }) - - class PWMConfig extends Config(new WithPWM ++ new BaseExampleConfig) -``` - -Now we can test that the PWM is working. The test program is in tests/pwm.c - -```c - #define PWM_PERIOD 0x2000 - #define PWM_DUTY 0x2008 - #define PWM_ENABLE 0x2010 - - static inline void write_reg(unsigned long addr, unsigned long data) - { - volatile unsigned long *ptr = (volatile unsigned long *) addr; - *ptr = data; - } - - static inline unsigned long read_reg(unsigned long addr) - { - volatile unsigned long *ptr = (volatile unsigned long *) addr; - return *ptr; - } - - int main(void) - { - write_reg(PWM_PERIOD, 20); - write_reg(PWM_DUTY, 5); - write_reg(PWM_ENABLE, 1); - } -``` - -This just writes out to the registers we defined earlier. The base of the -module's MMIO region is at 0x2000. This will be printed out in the address -map portion when you generated the verilog code. - -Compiling this program with make produces a `pwm.riscv` executable. - -Now with all of that done, we can go ahead and run our simulation. - - cd verisim - make CONFIG=PWMConfig - ./simulator-example-PWMConfig ../tests/pwm.riscv - -## Adding a DMA port - -In the example above, we gave allowed the processor to communicate with the -peripheral through MMIO. However, for IO devices (like a disk or network -driver), we may want to have the device write directly to the coherent -memory system instead. To add a device like that, you would do the following. - -```scala - class DMADevice(implicit p: Parameters) extends LazyModule { - val node = TLClientNode(TLClientParameters( - name = "dma-device", sourceId = IdRange(0, 1))) - - lazy val module = new DMADeviceModule(this) - } - - class DMADeviceModule(outer: DMADevice) extends LazyModuleImp(outer) { - val io = IO(new Bundle { - val mem = outer.node.bundleOut - val ext = new ExtBundle - }) - - // ... rest of the code ... - } - - trait HasPeripheryDMA extends HasSystemNetworks { - implicit val p: Parameters - - val dma = LazyModule(new DMADevice) - - fsb.node := dma.node - } - - trait HasPeripheryDMAModuleImp extends LazyMultiIOModuleImp { - val ext = IO(new ExtBundle) - ext <> outer.dma.module.io.ext - } -``` - -The `ExtBundle` contains the signals we connect off-chip that we get data from. -The DMADevice also has a Tilelink client port that we connect into the L1-L2 -crossbar through the front-side buffer (fsb). The sourceId variable given in -the TLClientNode instantiation determines the range of ids that can be used -in acquire messages from this device. Since we specified [0, 1) as our range, -only the ID 0 can be used. - -## Adding a RoCC accelerator - -Besides peripheral devices, a RocketChip-based SoC can also be customized with -coprocessor accelerators. Each core can have up to four accelerators that -are controlled by custom instructions and share resources with the CPU. - -### A RoCC instruction - -Coprocessor instructions have the following form. - - customX rd, rs1, rs2, funct - -The X will be a number 0-3, and determines the opcode of the instruction, -which controls which accelerator an instruction will be routed to. -The `rd`, `rs1`, and `rs2` fields are the register numbers of the destination -register and two source registers. The `funct` field is a 7-bit integer that -the accelerator can use to distinguish different instructions from each other. - -### Creating an accelerator - -RoCC accelerators are lazy modules that extend the LazyRoCC class. -Their implementation should extends the LazyRoCCModule class. - -```scala - class CustomAccelerator(opcodes: OpcodeSet) - (implicit p: Parameters) extends LazyRoCC(opcodes) { - override lazy val module = new CustomAcceleratorModule(this) - } - - class CustomAcceleratorModule(outer: CustomAccelerator) - extends LazyRoCCModuleImp(outer) { - val cmd = Queue(io.cmd) - // The parts of the command are as follows - // inst - the parts of the instruction itself - // opcode - // rd - destination register number - // rs1 - first source register number - // rs2 - second source register number - // funct - // xd - is the destination register being used? - // xs1 - is the first source register being used? - // xs2 - is the second source register being used? - // rs1 - the value of source register 1 - // rs2 - the value of source register 2 - ... - } -``` - -The `opcodes` parameter for `LazyRoCC` is -the set of custom opcodes that will map to this accelerator. More on this -in the next subsection. - -The `LazyRoCC` class contains two TLOutputNode instances, `atlNode` and `tlNode`. -The former connects into a tile-local arbiter along with the backside of the -L1 instruction cache. The latter connects directly to the L1-L2 crossbar. -The corresponding Tilelink ports in the module implementation's IO bundle -are `atl` and `tl`, respectively. - -The other interfaces available to the accelerator are `mem`, which provides -access to the L1 cache; `ptw` which provides access to the page-table walker; -the `busy` signal, which indicates when the accelerator is still handling an -instruction; and the `interrupt` signal, which can be used to interrupt the CPU. - -Look at the examples in rocket-chip/src/main/scala/tile/LazyRocc.scala for -detailed information on the different IOs. - -### Adding RoCC accelerator to Config - -RoCC accelerators can be added to a core by overriding the `BuildRoCC` parameter -in the configuration. This takes a sequence of functions producing `LazyRoCC` -objects, one for each accelerator you wish to add. - -For instance, if we wanted to add the previously defined accelerator and -route custom0 and custom1 instructions to it, we could do the following. - -```scala - class WithCustomAccelerator extends Config((site, here, up) => { - case BuildRoCC => Seq((p: Parameters) => LazyModule( - new CustomAccelerator(OpcodeSet.custom0 | OpcodeSet.custom1)(p))) - }) - - class CustomAcceleratorConfig extends Config( - new WithCustomAccelerator ++ new DefaultExampleConfig) -``` - -## Adding a submodule - -While developing, you want to include Chisel code in a submodule so that it -can be shared by different projects. To add a submodule to the project -template, make sure that your project is organized as follows. - - yourproject/ - build.sbt - src/main/scala/ - YourFile.scala - -Put this in a git repository and make it accessible. Then add it as a submodule -to the project template. - - git submodule add https://git-repository.com/yourproject.git - -Then add `yourproject` to the project-template build.sbt file. - -```scala - lazy val yourproject = project.settings(commonSettings).dependsOn(rocketchip) -``` - -You can then import the classes defined in the submodule in a new project if -you add it as a dependency. For instance, if you want to use this code in -the `example` project, change the final line in build.sbt to the following. - -```scala - lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) -``` - -Finally, add `yourproject` to the `PACKAGES` variable in the `Makefrag`. This will allow make to detect -that your source files have changed when building the verilog/firrtl files. +[hwacha]:http://hwacha.org +[hammer]:https://github.com/ucb-bar/hammer +[firesim]:https://fires.im +[ucb-bar]: http://bar.eecs.berkeley.edu +[eecs]: https://eecs.berkeley.edu +[berkeley]: https://berkeley.edu +[riscv]: https://riscv.org/ +[rocket-chip]: https://github.com/freechipsproject/rocket-chip +[boom]: https://github.com/ucb-bar/riscv-boom From 92a7e707502adfb8f8689d02c8c8c4b4e75eba59 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 28 May 2019 17:42:05 -0700 Subject: [PATCH 32/36] fix rocketchip link --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 559431f2..2bf6a212 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,7 @@ To get started using REBAR, see the documentation on the REBAR documentation sit REBAR is an open source starter template for your custom Chisel project. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -It contains processor cores ([Rocket][rocket], [BOOM][boom]), accelerators ([Hwacha][hwacha]), FPGA simulation tools ([FireSim][firesim]), ASIC tools ([HAMMER][hammer]) and other tooling to help create a full featured SoC. +It contains processor cores ([Rocket][rocket-chip], [BOOM][boom]), accelerators ([Hwacha][hwacha]), FPGA simulation tools ([FireSim][firesim]), ASIC tools ([HAMMER][hammer]) and other tooling to help create a full featured SoC. REBAR is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. ## Resources From 194dd1917a74471a81177b3e3e85d3bde41b344b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 28 May 2019 22:48:40 -0700 Subject: [PATCH 33/36] add initial setup instructions --- docs/Getting-Started/Initial-Repo-Setup.rst | 31 +++++++++++++++++++++ docs/Getting-Started/index.rst | 1 + 2 files changed, 32 insertions(+) create mode 100644 docs/Getting-Started/Initial-Repo-Setup.rst diff --git a/docs/Getting-Started/Initial-Repo-Setup.rst b/docs/Getting-Started/Initial-Repo-Setup.rst new file mode 100644 index 00000000..28afbcb1 --- /dev/null +++ b/docs/Getting-Started/Initial-Repo-Setup.rst @@ -0,0 +1,31 @@ +Initial Repository Setup +======================================================== + +Checking out the sources +------------------------ + +After cloning this repo, you will need to initialize all of the submodules. + +.. code-block:: shell + git clone https://github.com/ucb-bar/project-template.git + cd project-template + ./scripts/init-submodules-no-riscv-tools.sh + +Building a Toolchain +------------------------ + +The `toolchains` directory contains toolchains that include a cross-compiler toolchain, frontend server, and proxy kernel, which you will need in order to compile code to RISC-V instructions and run them on your design. +Currently there are two toolchains, one for normal RISC-V programs, and another for Hwacha (``esp-tools``). +There are detailed instructions at https://github.com/riscv/riscv-tools to install the ``riscv-tools`` toolchain, however, the instructions are similar for the Hwacha ``esp-tools`` toolchain. +But to get a basic installation, just the following steps are necessary. + +.. code-block:: shell + ./scripts/build-toolchains.sh riscv # for a normal risc-v toolchain + + # OR + + ./scripts/build-toolchains.sh hwacha # for a hwacha modified risc-v toolchain + +Once the script is run, a ``env.sh`` file is emitted at sets the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables. +You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables. +These variables need to be set for the make system to work properly. diff --git a/docs/Getting-Started/index.rst b/docs/Getting-Started/index.rst index 61a77dec..be6aa1e3 100644 --- a/docs/Getting-Started/index.rst +++ b/docs/Getting-Started/index.rst @@ -16,5 +16,6 @@ Hit next to get started! REBAR-Basics Configs-Parameters-Mixins Adding-An-Accelerator-Tutorial + Initial-Repo-Setup Running-A-Simulation rebar-generator-mixins From 3a1dbf89834508edccc340c47851d89765fdea36 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 28 May 2019 23:04:53 -0700 Subject: [PATCH 34/36] make sure code blocks appear --- docs/Getting-Started/Initial-Repo-Setup.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/Getting-Started/Initial-Repo-Setup.rst b/docs/Getting-Started/Initial-Repo-Setup.rst index 28afbcb1..58a40d56 100644 --- a/docs/Getting-Started/Initial-Repo-Setup.rst +++ b/docs/Getting-Started/Initial-Repo-Setup.rst @@ -7,6 +7,7 @@ Checking out the sources After cloning this repo, you will need to initialize all of the submodules. .. code-block:: shell + git clone https://github.com/ucb-bar/project-template.git cd project-template ./scripts/init-submodules-no-riscv-tools.sh @@ -20,6 +21,7 @@ There are detailed instructions at https://github.com/riscv/riscv-tools to insta But to get a basic installation, just the following steps are necessary. .. code-block:: shell + ./scripts/build-toolchains.sh riscv # for a normal risc-v toolchain # OR From 5ef1d449aa4dd920dc8ca2ed5240daad61ebe815 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Fri, 31 May 2019 17:30:10 +0200 Subject: [PATCH 35/36] gitmodules: now only use https instead of ssh git submodule init --recursive --init would result in a public key error Signed-off-by: Bastian Koppelmann --- .gitmodules | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.gitmodules b/.gitmodules index 698c53b9..22b438a6 100644 --- a/.gitmodules +++ b/.gitmodules @@ -21,13 +21,13 @@ url = https://github.com/ucb-bar/esp-tools.git [submodule "tools/torture"] path = tools/torture - url = git@github.com:ucb-bar/riscv-torture.git + url = https://github.com/ucb-bar/riscv-torture.git [submodule "generators/boom"] path = generators/boom - url = git@github.com:riscv-boom/riscv-boom.git + url = https://github.com/riscv-boom/riscv-boom.git [submodule "generators/sifive-blocks"] path = generators/sifive-blocks - url = git@github.com:sifive/sifive-blocks.git + url = https://github.com/sifive/sifive-blocks.git [submodule "generators/hwacha"] path = generators/hwacha - url = git@github.com:ucb-bar/hwacha.git + url = https://github.com/ucb-bar/hwacha.git From ed37f1d01bc6850be87cf7f6226159bcb16e3c8f Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Fri, 31 May 2019 17:31:26 +0200 Subject: [PATCH 36/36] gitignore: add env.sh and riscv-tools-install Signed-off-by: Bastian Koppelmann --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 551a8e97..8450e9b8 100644 --- a/.gitignore +++ b/.gitignore @@ -7,4 +7,6 @@ target *.swp .idea .DS_Store +env.sh +riscv-tools-install tags