From 873131c0c711962b4169f38e7cdc55ca147d7a6c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 4 Oct 2022 08:12:48 -0700 Subject: [PATCH] Initial CIRCT integration [ci skip] --- common.mk | 41 ++++++++++++++++++++++++++++++++++++----- variables.mk | 10 ++++++---- 2 files changed, 42 insertions(+), 9 deletions(-) diff --git a/common.mk b/common.mk index fe2d7e7b..9e39ccf0 100644 --- a/common.mk +++ b/common.mk @@ -110,6 +110,15 @@ $(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_D --top-module $(MODEL_PACKAGE).$(MODEL) \ --legacy-configs $(CONFIG_PACKAGE):$(CONFIG) \ $(EXTRA_CHISEL_OPTIONS)) + sed -i '1d' $(ANNO_FILE) + echo "[" >> t.json + echo "{" >> t.json + echo " \"class\": \"sifive.enterprise.firrtl.ModuleHierarchyAnnotation\"," >> t.json + echo " \"filename\": \"./mod-he.json\"" >> t.json + echo "}," >> t.json + mv $(ANNO_FILE) t2.json + cat t.json t2.json > $(ANNO_FILE) + rm t.json t2.json .PHONY: firrtl firrtl: $(FIRRTL_FILE) @@ -117,11 +126,7 @@ firrtl: $(FIRRTL_FILE) ######################################################################################### # create verilog files rules and variables ######################################################################################### -REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF) -HARNESS_CONF_FLAGS = -thconf $(HARNESS_SMEMS_CONF) - -TOP_TARGETS = $(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes) -HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes) +CIRCT_TARGETS = $(VSRC_SMEMS_FILE) $(VSRC_MODH_JSON) # DOC include start: FirrtlCompiler $(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) @@ -145,6 +150,32 @@ $(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) --log-level $(FIRRTL_LOGLEVEL) \ $(EXTRA_FIRRTL_OPTIONS)) touch $(sim_top_blackboxes) $(sim_harness_blackboxes) + +# NOTE: These *_temp intermediate targets will get removed in favor of make 4.3 grouped targets (&: operator) +.INTERMEDIATE: firrtl_temp +$(CIRCT_TARGETS): firrtl_temp + @echo "" > /dev/null + +firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) + $(SCRATCH_HOME)/circt/build/bin/firtool \ + --export-module-hierarchy \ + --emit-metadata \ + --format=fir \ + -warn-on-unprocessed-annotations \ + -verify-each=false \ + -dedup \ + --annotation-file=$(ANNO_FILE) \ + --disable-annotation-classless \ + --disable-annotation-unknown \ + --lowering-options=disallowPackedArrays,emittedLineLength=8192,noAlwaysComb,disallowLocalVariables \ + --repl-seq-mem \ + --repl-seq-mem-circuit=$(MODEL) \ + --repl-seq-mem-file=$(VSRC_SMEMS_FILE) \ + --split-verilog \ + -o $(VSRC_DUMP) \ + $(FIRRTL_FILE) +# touch $(sim_top_blackboxes) $(sim_harness_blackboxes) +>>>>>>> 9306c549 (Initial CIRCT integration [ci skip]) # DOC include end: FirrtlCompiler # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs diff --git a/variables.mk b/variables.mk index 22848145..2b0f405e 100644 --- a/variables.mk +++ b/variables.mk @@ -146,6 +146,10 @@ endif FIRRTL_FILE ?= $(build_dir)/$(long_name).fir ANNO_FILE ?= $(build_dir)/$(long_name).anno.json +VSRC_DUMP ?= $(build_dir)/vsrc +VSRC_SMEMS_FILE ?= $(VSRC_DUMP)/$(long_name).mems.v +VSRC_MODH_JSON ?= $(VSRC_DUMP)/mod-he.json + TOP_FILE ?= $(build_dir)/$(long_name).top.v TOP_FIR ?= $(build_dir)/$(long_name).top.fir TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json @@ -240,10 +244,8 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc # sources needed to run simulators ######################################################################################### sim_vsrcs = \ - $(TOP_FILE) \ - $(HARNESS_FILE) \ - $(TOP_SMEMS_FILE) \ - $(HARNESS_SMEMS_FILE) + $(VSRC_SMEMS_FILE) \ + $(VSRC_MODH_JSON) ######################################################################################### # assembly/benchmark variables