From 885c5f74db287d63411e4c0b1ca500c7985287a0 Mon Sep 17 00:00:00 2001
From: abejgonzalez <abe.j.gonza@gmail.com>
Date: Wed, 17 Apr 2019 17:08:08 -0700
Subject: [PATCH] bump boom/firrtl | support building boom | update genfiles in
 simulator to make rv32 bootrom | misc cleanup

---
 generators/boom                        | 2 +-
 sims/verisim/Makefile                  | 2 +-
 sims/vsim/Makefile                     | 2 +-
 src/main/scala/example/Simulator.scala | 1 +
 tools/firrtl                           | 2 +-
 5 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/generators/boom b/generators/boom
index f1caea81..4cd347ed 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit f1caea81c6daa183c8a9fc82d2a5dee1625640ad
+Subproject commit 4cd347ed51f8bdf98d2d1868cf1530d845539613
diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile
index ee04e656..89d9c6e8 100644
--- a/sims/verisim/Makefile
+++ b/sims/verisim/Makefile
@@ -89,5 +89,5 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 # general cleanup rule
 #########################################################################################
 .PHONY: clean
-clean: clean-scala
+clean:
 	rm -rf $(build_dir) $(sim_prefix)-*
diff --git a/sims/vsim/Makefile b/sims/vsim/Makefile
index 3742a895..be8fd716 100644
--- a/sims/vsim/Makefile
+++ b/sims/vsim/Makefile
@@ -93,5 +93,5 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 # general cleanup rule
 #########################################################################################
 .PHONY: clean
-clean: clean-scala
+clean:
 	rm -rf $(build_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h
diff --git a/src/main/scala/example/Simulator.scala b/src/main/scala/example/Simulator.scala
index 240f930f..09c2cd77 100644
--- a/src/main/scala/example/Simulator.scala
+++ b/src/main/scala/example/Simulator.scala
@@ -101,6 +101,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
   def writeBootrom(): Unit = {
     firrtl.FileUtils.makeDirectory("./bootrom/")
     writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/")
+    writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/")
   }
 
   def writeFiles(cfg: GenerateSimConfig): Unit = {
diff --git a/tools/firrtl b/tools/firrtl
index 2272044c..bf66997b 160000
--- a/tools/firrtl
+++ b/tools/firrtl
@@ -1 +1 @@
-Subproject commit 2272044c6ab46b5148c39c124e66e1a8e9073a24
+Subproject commit bf66997b1a2438a322cd619ca2b6aeb0f0ac0ba0