Support variable VLEN cosim

generators/chipyard/src/main/resources/csrc/cospike.cc

@@ -42,6 +42,7 @@ extern std::map<long long int, backing_data_t> backing_mem_data;
 
 typedef struct system_info_t {
   std::string isa;
+  int vlen;
   int pmpregions;
   uint64_t mem0_base;
   uint64_t mem0_size;
@@ -89,7 +90,7 @@ static std::vector<std::pair<reg_t, abstract_mem_t*>> make_mems(const std::vecto
   return mems;
 }
 
-extern "C" void cospike_set_sysinfo(char* isa, char* priv, int pmpregions,
+extern "C" void cospike_set_sysinfo(char* isa, int vlen, char* priv, int pmpregions,
                                     long long int mem0_base, long long int mem0_size,
                                     int nharts,
                                     char* bootrom
@@ -98,6 +99,7 @@ extern "C" void cospike_set_sysinfo(char* isa, char* priv, int pmpregions,
     info = new system_info_t;
     // technically the targets aren't zicntr compliant, but they implement the zicntr registers
     info->isa = std::string(isa) + "_zicntr";
+    info->vlen = vlen;
     info->priv = std::string(priv);
     info->pmpregions = pmpregions;
     info->mem0_base = mem0_base;
@@ -133,11 +135,12 @@ extern "C" void cospike_cosim(long long int cycle,
     for (int i = 0; i < info->nharts; i++)
       hartids.push_back(i);
 
+    std::string visa = "vlen:" + std::to_string(info->vlen ? info->vlen : 128) + ",elen:64";
     cfg = new cfg_t(std::make_pair(0, 0),
                     nullptr,
                     info->isa.c_str(),
                     info->priv.c_str(),
-                    "vlen:128,elen:64",
+                    visa.c_str(),
                     false,
                     endianness_little,
                     info->pmpregions,
@@ -420,6 +423,7 @@ extern "C" void cospike_cosim(long long int cycle,
     bool scalar_wb = false;
     bool vector_wb = false;
     uint32_t vector_cnt = 0;
+    std::vector<reg_t> vector_rds;
     
     for (auto &regwrite : log) {
 
@@ -446,15 +450,16 @@ extern "C" void cospike_cosim(long long int cycle,
                            lr_read ||
                            (tohost_addr && mem_read_addr == tohost_addr) ||
                            (fromhost_addr && mem_read_addr == fromhost_addr)));
+      //COSPIKE_PRINTF("register write type %d\n", type);
       // check the type is compliant with writeback first
       if ((type == 0 || type == 1))
         scalar_wb = true;
       if (type == 2) {
+        vector_rds.push_back(rd);
         vector_wb = true;
       }
       if (type == 3) continue;
 
-
       if ((rd != 0 && type == 0) || type == 1) {
         // Override reads from some CSRs
         uint64_t csr_addr = (insn >> 20) & 0xfff;
@@ -496,5 +501,8 @@ extern "C" void cospike_cosim(long long int cycle,
       //   exit(-1);
       // }
     }
+    for (auto &a : vector_rds) {
+      COSPIKE_PRINTF("vector writeback to v%d\n", a);
+    }
   }
 }

generators/chipyard/src/main/resources/vsrc/cospike.v

@@ -1,5 +1,6 @@
 import "DPI-C" function void cospike_set_sysinfo(
                                                  input string  isa,
+                                                 input int     vlen,
                                                  input string  priv,
                                                  input int     pmpregions,
                                                  input longint mem0_base,
@@ -25,6 +26,7 @@ import "DPI-C" function void cospike_cosim(input longint cycle,
 module SpikeCosim  #(
                      parameter ISA,
                      parameter PRIV,
+                     parameter VLEN,
                      parameter PMPREGIONS,
                      parameter MEM0_BASE,
                      parameter MEM0_SIZE,
@@ -59,7 +61,7 @@ module SpikeCosim  #(
                                          );
 
    initial begin
-      cospike_set_sysinfo(ISA, PRIV, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM);
+      cospike_set_sysinfo(ISA, VLEN, PRIV, PMPREGIONS, MEM0_BASE, MEM0_SIZE, NHARTS, BOOTROM);
    end;
 
    always @(posedge clock) begin

generators/chipyard/src/main/scala/Cospike.scala

@@ -14,6 +14,7 @@ import testchipip.TileTraceIO
 
 case class SpikeCosimConfig(
   isa: String,
+  vlen: Int,
   priv: String,
   pmpregions: Int,
   mem0_base: BigInt,
@@ -25,6 +26,7 @@ case class SpikeCosimConfig(
 
 class SpikeCosim(cfg: SpikeCosimConfig) extends BlackBox(Map(
   "ISA" -> StringParam(cfg.isa),
+  "VLEN" -> IntParam(cfg.vlen),
   "PRIV" -> StringParam(cfg.priv),
   "PMPREGIONS" -> IntParam(cfg.pmpregions),
   "MEM0_BASE" -> IntParam(cfg.mem0_base),

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -365,6 +365,7 @@ class WithCospike extends ComposeHarnessBinder({
     val tiles = chipyardSystem.tiles
     val cfg = SpikeCosimConfig(
       isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
+      vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0),
       priv = tiles.headOption.map(t => if (t.usingUser) "MSU" else if (t.usingSupervisor) "MS" else "M").getOrElse(""),
       mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0)),
       mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0)),