diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index 3dd380ea..89105d78 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -30,7 +30,7 @@ import scala.reflect.{ClassTag}
 
 import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
 
-class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
+class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
   (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => {
   // (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
     // ports.map {
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
   }
 })
 
-class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
+class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
   (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
   // (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
     // UARTAdapter.connect(ports)(system.p)
@@ -70,4 +70,4 @@ class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
     // IOBUF(th.ck_io(3),  ports.rxd)
     Nil
   }
-})
\ No newline at end of file
+})