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Merge branch 'graphics' of https://github.com/hansungk/chipyard into graphics

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This commit is contained in:
Richard Yan
2024-08-06 02:36:03 -07:00
parent c1b3fd99ff 8b9fee03bb
commit 89788cbde4
3 changed files with 4 additions and 3 deletions
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4
generators/chipyard/src/main/scala/config/RadianceConfigs.scala
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@@ -34,8 +34,8 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn
// ---------------- // ----------------
class RadianceBaseConfig(argsBinFilename: String = "args.bin") extends Config( class RadianceBaseConfig(argsBinFilename: String = "args.bin") extends Config(
// NOTE: when changing these, remember to change +define+NUM_CORES/THREADS/WARPS in // NOTE: when changing these, remember to change NUM_CORES/THREADS/WARPS in
// radiance.mk as well! // the verilog source as well!
new radiance.subsystem.WithSimtConfig(nWarps = 8, nCoreLanes = 8, nMemLanes = 8, nSrcIds = 32) ++ new radiance.subsystem.WithSimtConfig(nWarps = 8, nCoreLanes = 8, nMemLanes = 8, nSrcIds = 32) ++
new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
new WithExtMemSize(BigInt("80000000", 16)) ++ new WithExtMemSize(BigInt("80000000", 16)) ++

2
generators/radiance

Submodule generators/radiance updated: 37fd0c6200...33aa4e08db

1
vlsi/Makefile
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@@ -87,6 +87,7 @@ ifneq ($(EXT_FILELISTS),)
cat $(EXT_FILELISTS) >> $(VLSI_RTL) cat $(EXT_FILELISTS) >> $(VLSI_RTL)
endif endif
endif endif
$(vlsi_dir)/make_syn_f.sh $(build_dir)
######################################################################################### #########################################################################################
# srams # srams