add operand roms, point testchipip to fork, bump rocket

.gitmodules

@@ -3,7 +3,7 @@
 	url = https://github.com/hansungk/rocket-chip.git
 [submodule "testchipip"]
 	path = generators/testchipip
-	url = https://github.com/ucb-bar/testchipip.git
+	url = https://github.com/richardyrh/testchipip.git
 [submodule "barstools"]
 	path = tools/barstools
 	url = https://github.com/ucb-bar/barstools.git

generators/chipyard/src/main/scala/System.scala

@@ -32,7 +32,7 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
 
   val bootROM  = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
   val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
-  p(RadianceArgsROMLocated()).foreach { BootROM.attachArgs(_, this, CBUS) }
+  p(RadianceROMsLocated()).foreach { BootROM.attachROM(_, this, CBUS) }
 
   // If there is no bootrom, the tile reset vector bundle will be tied to zero
   if (bootROM.isEmpty) {

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -1,9 +1,12 @@
 package chipyard
 
+import chipyard.config.{AbstractConfig, WithBootROM}
+import chipyard.stage.phases.TargetDirKey
 import org.chipsalliance.cde.config.{Config, Field}
 import freechips.rocketchip.diplomacy.AsynchronousCrossing
-import freechips.rocketchip.devices.tilelink.{RadianceArgsROMLocated, RadianceArgsROMParams}
+import freechips.rocketchip.devices.tilelink.{BootROMLocated, RadianceROMParams, RadianceROMsLocated}
-import freechips.rocketchip.subsystem.WithExtMemSize
+import freechips.rocketchip.subsystem.{WithBootROMFile, WithExtMemSize}
+import freechips.rocketchip.tile.XLen
 // --------------
 // Rocket Configs
 // --------------
@@ -13,9 +16,23 @@ class RocketConfig extends Config(
   new chipyard.config.AbstractConfig)
 
 
-class WithRadArgsROM(filename: String) extends Config((site, here, up) => {
+class WithRadROMs(address: BigInt, size: Int, filename: String) extends Config((site, here, up) => {
-  case RadianceArgsROMLocated() => up(RadianceArgsROMLocated()).map(_.copy(
+  case RadianceROMsLocated() => up(RadianceROMsLocated()) ++
-    contentFileName = filename))
+    Seq(RadianceROMParams(
+      address = address,
+      size = size,
+      contentFileName = filename
+    ))
+})
+
+class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigInt = 0x10100) extends Config((site, here, up) => {
+  case BootROMLocated(x) => up(BootROMLocated(x), site)
+    .map(_.copy(
+      address = address,
+      size = size,
+      hang = hang,
+      contentFileName = s"${site(TargetDirKey)}/bootrom.radiance.rv${site(XLen)}.img"
+    ))
 })
 
 class RadianceConfig extends Config(
@@ -25,8 +42,11 @@ class RadianceConfig extends Config(
   // new testchipip.WithSbusScratchpad(banks=2) ++
   // new testchipip.WithMbusScratchpad(banks=2) ++
   new WithExtMemSize(BigInt("80000000", 16)) ++
-  new WithRadArgsROM("sims/vcs/args.bin") ++
+  new WithRadBootROM() ++
-  new chipyard.config.AbstractConfig)
+  new WithRadROMs(0x7FFF0000L, 0x10000, "sims/vcs/args.bin") ++
+  new WithRadROMs(0x20000L, 0x8000, "sims/vcs/op_a.bin") ++
+  new WithRadROMs(0x28000L, 0x8000, "sims/vcs/op_b.bin") ++
+  new AbstractConfig)
 
 class TinyRocketConfig extends Config(
   new chipyard.iobinders.WithDontTouchIOBinders(false) ++         // TODO FIX: Don't dontTouch the ports