From 8b3fef85cefdb98938e85e5cc01d7f529ba51b15 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 20 May 2019 17:44:47 -0700 Subject: [PATCH] first attempt at heter. port --- .../main/scala/BoomAndRocketSubsystem.scala | 94 ++++++++++++++ .../example/src/main/scala/ConfigMixins.scala | 66 ++++++++++ .../example/src/main/scala/Configs.scala | 120 +++++++++++++++++- .../scala/ExampleBoomAndRocketSystem.scala | 62 +++++++++ .../example/src/main/scala/TestHarness.scala | 35 +++++ generators/example/src/main/scala/Top.scala | 57 +++++++++ variables.mk | 12 ++ 7 files changed, 444 insertions(+), 2 deletions(-) create mode 100644 generators/example/src/main/scala/BoomAndRocketSubsystem.scala create mode 100644 generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala diff --git a/generators/example/src/main/scala/BoomAndRocketSubsystem.scala b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala new file mode 100644 index 00000000..275414ff --- /dev/null +++ b/generators/example/src/main/scala/BoomAndRocketSubsystem.scala @@ -0,0 +1,94 @@ +package example + +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo} + +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.amba.axi4._ + +import boom.system.{BoomTilesKey} + +trait HasBoomAndRocketTiles extends HasTiles + with CanHavePeripheryPLIC + with CanHavePeripheryCLINT + with HasPeripheryDebug +{ this: BaseSubsystem => + + val module: HasBoomAndRocketTilesModuleImp + + protected val rocketTileParams = p(RocketTilesKey) + protected val boomTileParams = p(BoomTilesKey) + private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) + private val boomCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), boomTileParams.size) + + // Make a tile and wire its nodes into the system, + // according to the specified type of clock crossing. + // Note that we also inject new nodes into the tile itself, + // also based on the crossing type. + val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) => + val rocket = LazyModule(new RocketTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) + + connectMasterPortsToSBus(rocket, crossing) + connectSlavePortsToCBus(rocket, crossing) + connectInterrupts(rocket, Some(debug), clintOpt, plicOpt) + + rocket + } + + println(s"DEBUG: Amount of rocket tiles: ${rocketTiles.length}") + + val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) => + val boomCore = LazyModule( + new boom.common.BoomTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name) + + connectMasterPortsToSBus(boomCore, crossing) + connectSlavePortsToCBus(boomCore, crossing) + connectInterrupts(boomCore, Some(debug), clintOpt, plicOpt) + + boomCore + } + + println(s"DEBUG: Amount of boom tiles: ${boomTiles.length}") + + val boomAndRocketTiles = rocketTiles ++ boomTiles + println(s"DEBUG: Amount of both tiles: ${boomAndRocketTiles.length}") + + def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++ + (boomTiles map { t => t.module.core.coreMonitorBundle}).toList + + def getOMRocketInterruptTargets(): Seq[OMInterruptTarget] = + boomAndRocketTiles.flatMap(c => c.cpuDevice.getInterruptTargets()) + + def getOMRocketCores(resourceBindingsMap: ResourceBindingsMap): Seq[OMComponent] = + boomAndRocketTiles.flatMap(c => c.cpuDevice.getOMComponents(resourceBindingsMap)) +} + +trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp + with HasPeripheryDebugModuleImp { + val outer: HasBoomAndRocketTiles +} + +class BoomAndRocketSubsystem(implicit p: Parameters) extends BaseSubsystem + with HasBoomAndRocketTiles { + val tiles = boomAndRocketTiles + override lazy val module = new BoomAndRocketSubsystemModuleImp(this) +} + +class BoomAndRocketSubsystemModuleImp[+L <: BoomAndRocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) + with HasBoomAndRocketTilesModuleImp { + tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => + wire.clock := clock + wire.reset := reset + wire.hartid := i.U + wire.reset_vector := global_reset_vector + } +} diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 5551a66d..02e4ea22 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -168,3 +168,69 @@ class WithGPIOBoomTop extends Config((site, here, up) => { top } }) + +// -------------------------------------- +// BOOM + Rocket Top Level System Parameter Mixins +// -------------------------------------- + +/** + * Class to specify a "plain" top level BOOM + Rocket system + */ +class WithNormalBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + Module(LazyModule(new BoomAndRocketTop()(p)).module) + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with PWM + */ +class WithPWMBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomAndRocketTopWithPWMTL()(p)).module) +}) + +/** + * Class to specify a top level BOOM + Rocket system with a PWM AXI4 + */ +class WithPWMAXI4BoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => + Module(LazyModule(new BoomAndRocketTopWithPWMAXI4()(p)).module) +}) + +/** + * Class to specify a top level BOOM + Rocket system with a block device + */ +class WithBlockDeviceModelBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) + top.connectBlockDeviceModel() + top + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with a simulator block device + */ +class WithSimBlockDeviceBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module) + top.connectSimBlockDevice(clock, reset) + top + } +}) + +/** + * Class to specify a top level BOOM + Rocket system with GPIO + */ +class WithGPIOBoomAndRocketTop extends Config((site, here, up) => { + case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => { + val top = Module(LazyModule(new BoomAndRocketTopWithGPIO()(p)).module) + for (gpio <- top.gpio) { + for (pin <- gpio.pins) { + pin.i.ival := false.B + } + } + top + } +}) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 68ca289c..97f08d62 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -106,10 +106,28 @@ class BlockDeviceModelBoomConfig extends Config( new WithBlockDeviceModelBoomTop ++ new BaseBoomConfig) +/** + * Slightly different looking configs since we need to override + * the `WithNBoomCores` with the DefaultBoomConfig params + */ class DualCoreBoomConfig extends Config( - // Core gets tacked onto existing list + new WithNormalBoomTop ++ + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ new boom.system.WithNBoomCores(2) ++ - new DefaultBoomConfig) + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.system.BaseConfig) + +class DualCoreSmallBoomConfig extends Config( + new WithNormalBoomTop ++ + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.WithSmallBooms ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(2) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.system.BaseConfig) class RV32BoomConfig extends Config( new WithBootROM ++ @@ -119,3 +137,101 @@ class GPIOBoomConfig extends Config( new WithGPIO ++ new WithGPIOBoomTop ++ new BaseBoomConfig) + +// --------------------- +// BOOM + Rocket Configs +// --------------------- + +//class BaseRocketConfig extends Config( +// new WithBootROM ++ +// new freechips.rocketchip.system.DefaultConfig) +// +//class DefaultRocketConfig extends Config( +// new WithNormalRocketTop ++ +// new BaseRocketConfig) +// +//class BaseConfig extends Config( +// new WithDefaultMemPort() ++ +// new WithDefaultMMIOPort() ++ +// new WithDefaultSlavePort() ++ +// new WithTimebase(BigInt(1000000)) ++ // 1 MHz +// new WithDTS("freechips,rocketchip-unknown", Nil) ++ +// new WithNExtTopInterrupts(2) ++ +// new BaseSubsystemConfig() +//) +// +//class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig) +// +////boom +// new WithRVC ++ +// new DefaultBoomConfig ++ +// new WithNBoomCores(1) ++ +// new WithoutTLMonitors ++ +// new freechips.rocketchip.system.BaseConfig) + +class BaseBoomAndRocketConfig extends Config( + new WithBootROM ++ + new boom.common.WithRVC ++ + new boom.common.DefaultBoomConfig ++ + new boom.system.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithoutTLMonitors ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +//class BaseBoomAndRocketConfig extends Config( +// new WithBootROM ++ +// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ +// new boom.system.BoomConfig) + +class SmallBaseBoomAndRocketConfig extends Config( + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new boom.system.SmallBoomConfig) + +class DefaultBoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class SmallDefaultBoomAndRocketConfig extends Config( + new WithNormalBoomAndRocketTop ++ + new SmallBaseBoomAndRocketConfig) + +class HwachaBoomAndRocketConfig extends Config( + new hwacha.DefaultHwachaConfig ++ + new DefaultBoomAndRocketConfig) + +class RoccBoomAndRocketConfig extends Config( + new WithRoccExample ++ + new DefaultBoomAndRocketConfig) + +class PWMBoomAndRocketConfig extends Config( + new WithPWMBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class PWMAXI4BoomAndRocketConfig extends Config( + new WithPWMAXI4BoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class SimBlockDeviceBoomAndRocketConfig extends Config( + new WithBlockDevice ++ + new WithSimBlockDeviceBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class BlockDeviceModelBoomAndRocketConfig extends Config( + new WithBlockDevice ++ + new WithBlockDeviceModelBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) + +class DualCoreBoomAndOneRocketConfig extends Config( + // Core gets tacked onto existing list + new boom.system.WithNBoomCores(2) ++ + new DefaultBoomAndRocketConfig) + +class RV32BoomAndNormalRocketConfig extends Config( + new WithBootROM ++ + new boom.system.SmallRV32UnifiedBoomConfig) + +class GPIOBoomAndRocketConfig extends Config( + new WithGPIO ++ + new WithGPIOBoomAndRocketTop ++ + new BaseBoomAndRocketConfig) diff --git a/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala new file mode 100644 index 00000000..cc7fd3db --- /dev/null +++ b/generators/example/src/main/scala/ExampleBoomAndRocketSystem.scala @@ -0,0 +1,62 @@ +package example + +import chisel3._ +import chisel3.internal.sourceinfo.{SourceInfo} + +import freechips.rocketchip.config.{Field, Parameters} +import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget} +import freechips.rocketchip.tile._ +import freechips.rocketchip.tilelink._ +import freechips.rocketchip.interrupts._ +import freechips.rocketchip.util._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.amba.axi4._ + +import boom.system.{BoomTilesKey} + +/** + * Example top with periphery devices and ports, and a BOOM subsystem + */ +class ExampleBoomAndRocketSystem(implicit p: Parameters) extends BoomAndRocketSubsystem + with HasAsyncExtInterrupts + with boom.system.CanHaveMisalignedMasterAXI4MemPort + with CanHaveMasterAXI4MMIOPort + with CanHaveSlaveAXI4Port + with HasPeripheryBootROM +{ + override lazy val module = new ExampleBoomAndRocketSystemModule(this) + + // The sbus masters the cbus; here we convert TL-UH -> TL-UL + sbus.crossToBus(cbus, NoCrossing) + + // The cbus masters the pbus; which might be clocked slower + cbus.crossToBus(pbus, SynchronousCrossing()) + + // The fbus masters the sbus; both are TL-UH or TL-C + FlipRendering { implicit p => + sbus.crossFromBus(fbus, SynchronousCrossing()) + } + + // The sbus masters the mbus; here we convert TL-C -> TL-UH + private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) + private val (in, out, halt) = coherenceManager(this) + if (nBanks != 0) { + sbus.coupleTo("coherence_manager") { in :*= _ } + mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } + } +} + +/** + * Example top module with periphery devices and ports, and a BOOM subsystem + */ +class ExampleBoomAndRocketSystemModule[+L <: ExampleBoomAndRocketSystem](_outer: L) extends BoomAndRocketSubsystemModuleImp(_outer) + with HasRTCModuleImp + with HasExtInterruptsModuleImp + with boom.system.CanHaveMisalignedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MMIOPortModuleImp + with CanHaveSlaveAXI4PortModuleImp + with HasPeripheryBootROMModuleImp + with DontTouch diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/example/src/main/scala/TestHarness.scala index b7120329..a517b6b8 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/example/src/main/scala/TestHarness.scala @@ -77,3 +77,38 @@ class BoomTestHarness(implicit val p: Parameters) extends Module { }) io.success := dut.connectSimSerial() } + +// -------------------------- +// BOOM + Rocket Test Harness +// -------------------------- + +case object BuildBoomAndRocketTop extends Field[(Clock, Bool, Parameters) => BoomAndRocketTopModule[BoomAndRocketTop]] + +class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { + val success = Output(Bool()) + }) + + // force Chisel to rename module + override def desiredName = "TestHarness" + + val dut = p(BuildBoomAndRocketTop)(clock, reset.toBool, p) + dut.debug := DontCare + dut.connectSimAXIMem() + dut.connectSimAXIMMIO() + dut.dontTouchPorts() + dut.tieOffInterrupts() + dut.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case core.ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case core.ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + io.success := dut.connectSimSerial() +} diff --git a/generators/example/src/main/scala/Top.scala b/generators/example/src/main/scala/Top.scala index 8a39e3d1..50e5d0c6 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/example/src/main/scala/Top.scala @@ -127,3 +127,60 @@ class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop class BoomTopWithGPIOModule(l: BoomTopWithGPIO) extends BoomTopModule(l) with HasPeripheryGPIOModuleImp + +// ------------------------------- +// BOOM + Rocket Top Level Systems +// ------------------------------- + +class BoomAndRocketTop(implicit p: Parameters) extends ExampleBoomAndRocketSystem + with HasNoDebug + with HasPeripherySerial { + override lazy val module = new BoomAndRocketTopModule(this) +} + +class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends ExampleBoomAndRocketSystemModule(l) + with HasRTCModuleImp + with HasNoDebugModuleImp + with HasPeripherySerialModuleImp + with DontTouch + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithPWMTL(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryPWMTL { + override lazy val module = new BoomAndRocketTopWithPWMTLModule(this) +} + +class BoomAndRocketTopWithPWMTLModule(l: BoomAndRocketTopWithPWMTL) extends BoomAndRocketTopModule(l) + with HasPeripheryPWMTLModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryPWMAXI4 { + override lazy val module = new BoomAndRocketTopWithPWMAXI4Module(this) +} + +class BoomAndRocketTopWithPWMAXI4Module(l: BoomAndRocketTopWithPWMAXI4) extends BoomAndRocketTopModule(l) + with HasPeripheryPWMAXI4ModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithBlockDevice(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryBlockDevice { + override lazy val module = new BoomAndRocketTopWithBlockDeviceModule(this) +} + +class BoomAndRocketTopWithBlockDeviceModule(l: BoomAndRocketTopWithBlockDevice) extends BoomAndRocketTopModule(l) + with HasPeripheryBlockDeviceModuleImp + +//--------------------------------------------------------------------------------------------------------- + +class BoomAndRocketTopWithGPIO(implicit p: Parameters) extends BoomAndRocketTop + with HasPeripheryGPIO { + override lazy val module = new BoomAndRocketTopWithGPIOModule(this) +} + +class BoomAndRocketTopWithGPIOModule(l: BoomAndRocketTopWithGPIO) + extends BoomAndRocketTopModule(l) + with HasPeripheryGPIOModuleImp diff --git a/variables.mk b/variables.mk index 0808003c..62cd35ce 100644 --- a/variables.mk +++ b/variables.mk @@ -50,6 +50,18 @@ ifeq ($(SUB_PROJECT),boomexample) TB ?= TestDriver TOP ?= BoomTop endif +# for a BOOM + Rocket based example system +ifeq ($(SUB_PROJECT),boomrocketexample) + SBT_PROJECT ?= example + MODEL ?= BoomAndRocketTestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= $(SBT_PROJECT) + CONFIG ?= DefaultBoomAndRocketConfig + CONFIG_PACKAGE ?= $(SBT_PROJECT) + GENERATOR_PACKAGE ?= $(SBT_PROJECT) + TB ?= TestDriver + TOP ?= BoomAndRocketTop +endif # for BOOM developers ifeq ($(SUB_PROJECT),boom) SBT_PROJECT ?= boom