VLSI docs revamp midpoint

2020-11-02 14:32:39 -08:00
parent 0f3f283893
commit 8bf23177d3
3 changed files with 130 additions and 1 deletions
--- a/docs/VLSI/Tutorial.rst
+++ b/docs/VLSI/Tutorial.rst
@@ -30,7 +30,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo

  * Verilog wrapper around the accelerator and dummy hard macro.

-* example.yml
+* example-asap7.yml

  * Hammer IR for this tutorial.