diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala
index 01d6c828..afe04eaf 100644
--- a/generators/chipyard/src/main/scala/Clocks.scala
+++ b/generators/chipyard/src/main/scala/Clocks.scala
@@ -134,8 +134,6 @@ object ClockingSchemeGenerators {
   val harnessDividedClock: ChipTop => Unit = { chiptop =>
     implicit val p = chiptop.p
 
-    require(false, "Divided clock is broken until we fix passing onchip clocks to TestHarness objects")
-
     val implicitClockSourceNode = ClockSourceNode(Seq(ClockSourceParameters()))
     chiptop.implicitClockSinkNode := implicitClockSourceNode