diff --git a/fpga/Makefile b/fpga/Makefile
index ab538116..835ffb59 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -21,9 +21,9 @@ SUB_PROJECT       := fpga
 SBT_PROJECT       := freedomPlatforms
 MODEL             := E300ArtyDevKitFPGAChip
 VLOG_MODEL        := E300ArtyDevKitFPGAChip
-MODEL_PACKAGE     := sifive.freedom.everywhere.e300artydevkit
+MODEL_PACKAGE     := chipyard.fpga
 CONFIG            := E300ArtyDevKitConfig
-CONFIG_PACKAGE    := sifive.freedom.everywhere.e300artydevkit
+CONFIG_PACKAGE    := chipyard.fpga
 GENERATOR_PACKAGE := chipyard
 TB                := none # unused
 TOP               := E300ArtyDevKitPlatform
@@ -34,7 +34,6 @@ BOARD ?= arty
 #########################################################################################
 # misc. directories
 #########################################################################################
-bootrom_dir := $(base_dir)/fpga/bootrom/xip
 fpga_dir := $(base_dir)/fpga/fpga-shells/xilinx
 fpga_common_script_dir := $(fpga_dir)/common/tcl
 
@@ -49,27 +48,7 @@ include $(base_dir)/common.mk
 all_vsrcs := \
 	$(sim_vsrcs) \
 	$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \
-	$(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v \
-	$(build_dir)/$(long_name).rom.v
-
-#########################################################################################
-# build rom for the fpga
-#########################################################################################
-# needed for bootrom makefile
-export BUILD_DIR=$(build_dir)
-export ROCKETCHIP_DIR
-export LONG_NAME=$(long_name)
-export ROMCONF=$(build_dir)/$(long_name).rom.conf
-
-romgen := $(build_dir)/$(long_name).rom.v
-$(romgen): $(sim_vsrcs)
-ifneq ($(bootrom_dir),"")
-	$(MAKE) -C $(bootrom_dir) romgen
-	mv $(build_dir)/rom.v $@
-endif
-
-.PHONY: romgen
-romgen: $(romgen)
+	$(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v
 
 #########################################################################################
 # vivado rules
@@ -119,6 +98,3 @@ prjx: $(prjx)
 .PHONY: clean
 clean:
 	rm -rf $(gen_dir)
-ifneq ($(bootrom_dir),"")
-	$(MAKE) -C $(bootrom_dir) clean
-endif
diff --git a/fpga/bootrom/xip/Makefile b/fpga/bootrom/xip/Makefile
deleted file mode 100644
index e51fd9c5..00000000
--- a/fpga/bootrom/xip/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-# RISCV environment variable must be set
-# needs the following variables
-# LONG_NAME
-# BUILD_DIR
-# ROCKETCHIP_DIR
-# ROMCONF
-
-CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
-OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
-CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g
-LFLAGS=-static -nostdlib
-
-dtb := $(BUILD_DIR)/$(LONG_NAME).dtb
-$(dtb): $(BUILD_DIR)/$(LONG_NAME).dts
-	dtc -I dts -O dtb -o $@ $<
-
-.PHONY: dtb
-dtb: $(dtb)
-
-elf := $(BUILD_DIR)/xip.elf
-$(elf): xip.S $(dtb)
-	$(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $<
-
-.PHONY: elf
-elf: $(elf)
-
-bin := $(BUILD_DIR)/xip.bin
-$(bin): $(elf)
-	$(OBJCOPY) -O binary $< $@
-
-.PHONY: bin
-bin: $(bin)
-
-hex := $(BUILD_DIR)/xip.hex
-$(hex): $(bin)
-	od -t x4 -An -w4 -v $< > $@
-
-.PHONY: hex
-hex: $(hex)
-
-romgen := $(BUILD_DIR)/rom.v
-$(romgen): $(hex)
-	$(ROCKETCHIP_DIR)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@
-
-.PHONY: romgen
-romgen: $(romgen)
-
-.PHONY: clean
-clean::
-	rm -rf $(hex) $(elf)
diff --git a/fpga/bootrom/xip/xip.S b/fpga/bootrom/xip/xip.S
deleted file mode 100644
index 7445f4c9..00000000
--- a/fpga/bootrom/xip/xip.S
+++ /dev/null
@@ -1,16 +0,0 @@
-// See LICENSE for license details.
-// Execute in place
-// Jump directly to XIP_TARGET_ADDR
-
-  .section .text.init
-  .option norvc
-  .globl _start
-_start:
-  csrr a0, mhartid
-  la a1, dtb
-  li t0, XIP_TARGET_ADDR
-  jr t0
-
-  .section .rodata
-dtb:
-  .incbin DEVICE_TREE
diff --git a/fpga/src/main/scala/arty/Config.scala b/fpga/src/main/scala/arty/Config.scala
index 11642164..73fb8b31 100644
--- a/fpga/src/main/scala/arty/Config.scala
+++ b/fpga/src/main/scala/arty/Config.scala
@@ -1,5 +1,5 @@
 // See LICENSE for license details.
-package sifive.freedom.everywhere.e300artydevkit
+package chipyard.fpga
 
 import freechips.rocketchip.config._
 import freechips.rocketchip.subsystem._
@@ -16,16 +16,7 @@ import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.i2c._
 
-// Default FreedomEConfig
-class DefaultFreedomEConfig extends Config (
-  new WithNBreakpoints(2)        ++
-  new WithNExtTopInterrupts(0)   ++
-  new WithJtagDTM                ++
-  new TinyConfig
-)
-
-// Freedom E300 Arty Dev Kit Peripherals
-class E300DevKitPeripherals extends Config((site, here, up) => {
+class E300DevKitExtra extends Config((site, here, up) => {
   case PeripheryGPIOKey => List(
     GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
   case PeripheryPWMKey => List(
@@ -47,19 +38,27 @@ class E300DevKitPeripherals extends Config((site, here, up) => {
     I2CParams(address = 0x10016000))
   case PeripheryMockAONKey =>
     MockAONParams(address = 0x10000000)
-  case MaskROMLocated(InSubsystem) => List(MaskROMParams(address = 0x10000, name = "BootROM"))
-  case BootROMLocated(InSubsystem) => None
+  case DTSTimebase => BigInt(32768)
+  case JtagDTMKey => new JtagDTMConfig (
+    idcodeVersion = 2,
+    idcodePartNum = 0x000,
+    idcodeManufId = 0x489,
+    debugIdleCycles = 5)
 })
 
-// Freedom E300 Arty Dev Kit Peripherals
 class E300ArtyDevKitConfig extends Config(
-  new E300DevKitPeripherals    ++
-  new DefaultFreedomEConfig().alter((site,here,up) => {
-    case DTSTimebase => BigInt(32768)
-    case JtagDTMKey => new JtagDTMConfig (
-      idcodeVersion = 2,
-      idcodePartNum = 0x000,
-      idcodeManufId = 0x489,
-      debugIdleCycles = 5)
-  })
-)
+  new E300DevKitExtra ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.With1TinyCore ++
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++
+  new freechips.rocketchip.subsystem.WithNoMemPort ++
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
+  new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
+  new freechips.rocketchip.subsystem.WithJtagDTM ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)
diff --git a/fpga/src/main/scala/arty/FPGAChip.scala b/fpga/src/main/scala/arty/FPGAChip.scala
index e0b0634c..26e75500 100644
--- a/fpga/src/main/scala/arty/FPGAChip.scala
+++ b/fpga/src/main/scala/arty/FPGAChip.scala
@@ -1,5 +1,5 @@
 // See LICENSE for license details.
-package sifive.freedom.everywhere.e300artydevkit
+package chipyard.fpga
 
 import Chisel._
 import chisel3.core.{attach}
diff --git a/fpga/src/main/scala/arty/Platform.scala b/fpga/src/main/scala/arty/Platform.scala
index 14c31628..514ff74c 100644
--- a/fpga/src/main/scala/arty/Platform.scala
+++ b/fpga/src/main/scala/arty/Platform.scala
@@ -1,5 +1,5 @@
 // See LICENSE for license details.
-package sifive.freedom.everywhere.e300artydevkit
+package chipyard.fpga
 
 import Chisel._
 
@@ -20,6 +20,8 @@ import sifive.blocks.devices.uart._
 import sifive.blocks.devices.i2c._
 import sifive.blocks.devices.pinctrl._
 
+import chipyard.{DigitalTop}
+
 //-------------------------------------------------------------------------
 // PinGen
 //-------------------------------------------------------------------------
@@ -51,8 +53,7 @@ class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
 //-------------------------------------------------------------------------
 
 class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
-  //val sys = Module(LazyModule(new E300ArtyDevKitSystem).module) This can be DigitalTop?
-  val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
+  val sys = Module(LazyModule(new DigitalTop).module)
   val io = new E300ArtyDevKitPlatformIO
 
   // This needs to be de-asserted synchronously to the coreClk.
diff --git a/fpga/src/main/scala/arty/System.scala b/fpga/src/main/scala/arty/System.scala
deleted file mode 100644
index 46e5c34e..00000000
--- a/fpga/src/main/scala/arty/System.scala
+++ /dev/null
@@ -1,57 +0,0 @@
-// See LICENSE for license details.
-package sifive.freedom.everywhere.e300artydevkit
-
-import Chisel._
-
-import freechips.rocketchip.config._
-import freechips.rocketchip.subsystem._
-import freechips.rocketchip.devices.debug._
-import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.system._
-
-import sifive.blocks.devices.mockaon._
-import sifive.blocks.devices.gpio._
-import sifive.blocks.devices.pwm._
-import sifive.blocks.devices.spi._
-import sifive.blocks.devices.uart._
-import sifive.blocks.devices.i2c._
-
-//-------------------------------------------------------------------------
-// E300ArtyDevKitSystem
-//-------------------------------------------------------------------------
-
-class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem
-    with HasPeripheryDebug
-    with HasPeripheryMockAON
-    with chipyard.example.CanHavePeripheryGCD
-    with HasPeripheryUART
-    with HasPeripherySPIFlash
-    with HasPeripherySPI
-    with HasPeripheryGPIO
-    with HasPeripheryPWM
-    with HasPeripheryI2C {
-  val bootROM  = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
-  val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
-
-  val maskROMResetVectorSourceNode = BundleBridgeSource[UInt]()
-  tileResetVectorNexusNode := maskROMResetVectorSourceNode
-
-  override lazy val module = new E300ArtyDevKitSystemModule(this)
-}
-
-class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
-  extends RocketSubsystemModuleImp(_outer)
-    with HasPeripheryDebugModuleImp
-    with chipyard.example.CanHavePeripheryGCDModuleImp
-    with HasPeripheryUARTModuleImp
-    with HasPeripherySPIModuleImp
-    with HasPeripheryGPIOModuleImp
-    with HasPeripherySPIFlashModuleImp
-    with HasPeripheryMockAONModuleImp
-    with HasPeripheryPWMModuleImp
-    with HasPeripheryI2CModuleImp {
-
-  // connect reset vector to 1st MaskROM
-  _outer.maskROMResetVectorSourceNode.bundle := p(MaskROMLocated(_outer.location))(0).address.U
-}
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index 81d0003d..160e6acf 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -13,6 +13,10 @@ import freechips.rocketchip.devices.tilelink._
 
 // DOC include start: DigitalTop
 class DigitalTop(implicit p: Parameters) extends ChipyardSystem
+  with sifive.blocks.devices.mockaon.HasPeripheryMockAON
+  with sifive.blocks.devices.spi.HasPeripherySPI
+  with sifive.blocks.devices.pwm.HasPeripheryPWM
+  with sifive.blocks.devices.i2c.HasPeripheryI2C
   with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
   with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
   with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
@@ -31,6 +35,10 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
 }
 
 class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
+  with sifive.blocks.devices.mockaon.HasPeripheryMockAONModuleImp
+  with sifive.blocks.devices.spi.HasPeripherySPIModuleImp
+  with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
+  with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
   with testchipip.CanHaveTraceIOModuleImp
   with testchipip.CanHavePeripheryBlockDeviceModuleImp
   with testchipip.CanHavePeripherySerialModuleImp