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update with changes [ci skip]

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2019-09-27 11:56:16 -07:00
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docs/Software/Spike.rst
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The RISC-V ISA Simulator (Spike)
=================================
Spike is the golden reference functional RISC-V ISA simulator.
Spike is the golden reference functional RISC-V ISA C++ sofware simulator.
It provides full system emulation or proxied emulation with the HTIF/FESVR.
It serves as a starting point for running software on a RISC-V target.
Here is a highlight of some of Spikes main features:
* Multiple ISAs: RV32IMAFDQCV extensions
* Multiple memory models: Weak Memory Ordering (WMO) and Total Store Ordering (TSO)
* Priveleged Spec: Machine, Supervisor, User modes (v1.11)
* Privileged Spec: Machine, Supervisor, User modes (v1.11)
* Debug Spec
* Single-step debugging with support for viewing memory/register contents
* Multiple CPU support
* JTAG support
* Highly extensible (add and test new instructions)
* And much more!
Spike comes pre-packaged in the RISC-V toolchain.
Spike comes pre-packaged in the RISC-V toolchain and is available on the path as ``spike``.
More information can be found in the `Spike repository <https://github.com/riscv/riscv-isa-sim>`__.