From 902d33ebd1448ef80c6596b8ffe887a8e8b412ed Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Wed, 20 Dec 2023 08:43:35 -0800
Subject: [PATCH] Add Arty100T JTAG

---
 fpga/src/main/scala/arty100t/Configs.scala    |  2 +-
 .../main/scala/arty100t/HarnessBinders.scala  | 25 ++++++++++++++++++-
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index fce9177d..df29d5af 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -27,6 +27,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
   new WithArty100TPMODUART ++
   new WithArty100TUARTTSI ++
   new WithArty100TDDRTL ++
+  new WithArty100TJTAG ++
   new WithNoDesignKey ++
   new testchipip.WithUARTTSIClient ++
   new chipyard.harness.WithSerialTLTiedOff ++
@@ -39,7 +40,6 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
   new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
   new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.config.WithNoDebug ++ // no jtag
   new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
   new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
   new freechips.rocketchip.subsystem.WithoutTLMonitors)
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index 6ad8defd..64676584 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -113,4 +113,27 @@ class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends Ha
 })
 
 // Maps the UART device to PMOD JD pins 3/7
-class WithArty100TPMODUART extends WithArty100TUART("E2", "F4")
+class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
+
+class WithArty100TJTAG extends HarnessBinder({
+  case (th: HasHarnessInstantiators, port: JTAGPort) => {
+    val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
+    val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
+    harnessIO <> port.io
+
+    ath.sdc.addClock("JTCK", IOPin(harnessIO.TCK), 10)
+    ath.sdc.addGroup(clocks = Seq("JTCK"))
+    ath.xdc.clockDedicatedRouteFalse(IOPin(harnessIO.TCK))
+    val packagePinsWithPackageIOs = Seq(
+      ("F4", IOPin(harnessIO.TCK)),
+      ("D2", IOPin(harnessIO.TMS)),
+      ("E2", IOPin(harnessIO.TDI)),
+      ("D4", IOPin(harnessIO.TDO))
+    )
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      ath.xdc.addPackagePin(io, pin)
+      ath.xdc.addIOStandard(io, "LVCMOS33")
+      ath.xdc.addPullup(io)
+    } }
+  }
+})