From 903971f32ff2eff3f5e9a83920b0bd1001ec5d66 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 8 Jun 2023 14:24:34 -0700 Subject: [PATCH] Add documentation page indicating existence of prefetchers --- docs/Generators/Prefetchers.rst | 9 +++++++++ docs/Generators/index.rst | 1 + .../chipyard/src/main/scala/config/RocketConfigs.scala | 6 +++--- scripts/tutorial-patches/build.sbt.patch | 2 +- 4 files changed, 14 insertions(+), 4 deletions(-) create mode 100644 docs/Generators/Prefetchers.rst diff --git a/docs/Generators/Prefetchers.rst b/docs/Generators/Prefetchers.rst new file mode 100644 index 00000000..550d22e7 --- /dev/null +++ b/docs/Generators/Prefetchers.rst @@ -0,0 +1,9 @@ +Prefetchers +==================================== + +The BAR-fetchers library is a collection of Chisel-implemented prefetchers, designed for compatibility with Chipyard and Rocket-Chip SoCs. +This package implements a generic prefetcher API, and example implementations of NextLine, Strided, and AMPM prefetchers. + +Prefetchers can be instantiated in front of a L1D HellaCache, or as TileLink nodes in front of some TileLink bus. + +An example configuration using prefetchers is found in the ``PrefetchingRocketConfig`` diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index cb8cdc47..b8f5df1b 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -34,3 +34,4 @@ so changes to the generators themselves will automatically be used when building NVDLA Sodor Mempress + Prefetchers diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index f71b6ea7..1c3884bc 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -128,9 +128,9 @@ class CustomIOChipTopRocketConfig extends Config( new chipyard.config.AbstractConfig) class PrefetchingRocketConfig extends Config( - new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher into L1D$ - new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher into L2 for L1I$ accesses - new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher into L2 for L1D$ accesses + new barf.WithHellaCachePrefetcher(Seq(0), barf.SingleStridedPrefetcherParams()) ++ // strided prefetcher, sits in front of the L1D$, monitors core requests to prefetching into the L1D$ + new barf.WithTLICachePrefetcher(barf.MultiNextLinePrefetcherParams()) ++ // next-line prefetcher, sits between L1I$ and L2, monitors L1I$ misses to prefetch into L2 + new barf.WithTLDCachePrefetcher(barf.SingleAMPMPrefetcherParams()) ++ // AMPM prefetcher, site between L1D$ and L2, monitors L1D$ misses to prefetch into L2 new chipyard.config.WithTilePrefetchers ++ // add TL prefetchers between tiles and the sbus new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index db81b052..dee7fcf5 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -10,7 +10,7 @@ index ec36a85f..c0c2849a 100644 +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, - constellation, mempress) + constellation, mempress, barf) @@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings)