Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate

.circleci/config.yml

@@ -287,6 +287,11 @@ jobs:
         steps:
             - prepare-rtl:
                 project-key: "chipyard-spiflashread"
+    prepare-chipyard-mmios:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                project-key: "chipyard-mmios"
     chipyard-rocket-run-tests:
         executor: main-env
         steps:
@@ -531,6 +536,10 @@ workflows:
                     - install-riscv-toolchain
                     - install-verilator
 
+            - prepare-chipyard-mmios:
+                requires:
+                    - install-riscv-toolchain
+
             # Run the respective tests
 
             # Run the example tests

.circleci/defaults.sh

@@ -47,23 +47,25 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
 
 # key value store to get the build strings
 declare -A mapping
-mapping["chipyard-rocket"]="SUB_PROJECT=chipyard"
+mapping["chipyard-rocket"]=""
-mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig"
+mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
-mapping["chipyard-streaming-fir"]="SUB_PROJECT=chipyard CONFIG=StreamingFIRRocketConfig"
+mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig"
-mapping["chipyard-streaming-passthrough"]="SUB_PROJECT=chipyard CONFIG=StreamingPassthroughRocketConfig"
+mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig"
-mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig"
+mapping["chipyard-hetero"]=" CONFIG=LargeBoomAndRocketConfig"
-mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig"
+mapping["chipyard-boom"]=" CONFIG=SmallBoomConfig"
-mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig"
+mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
-mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig"
+mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
-mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig"
+mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
-mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig"
+mapping["chipyard-ariane"]=" CONFIG=ArianeConfig"
-mapping["chipyard-spiflashread"]="SUB_PROJECT=chipyard CONFIG=LargeSPIFlashROMRocketConfig"
+mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
-mapping["chipyard-spiflashwrite"]="SUB_PROJECT=chipyard CONFIG=SmallSPIFlashRocketConfig"
+mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
-mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem"
+mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
-mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem"
+mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem"
-mapping["chipyard-nvdla"]="SUB_PROJECT=chipyard CONFIG=SmallNVDLARocketConfig"
+mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig TOP=TraceGenSystem"
+mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"
 mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
 mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"
 mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
 mapping["icenet"]="SUB_PROJECT=icenet"
 mapping["testchipip"]="SUB_PROJECT=testchipip"
+

README.md

@@ -39,7 +39,9 @@ If used for research, please cite Chipyard by the following publication:
   journal={IEEE Micro},
   title={Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs},
   year={2020},
-  pages={},
+  volume={40},
+  number={4},
+  pages={10-21},
   doi={10.1109/MM.2020.2996616},
   ISSN={1937-4143},
 }
@@ -76,7 +78,7 @@ These additional publications cover many of the internal components used in Chip
 [berkeley]: https://berkeley.edu
 [riscv]: https://riscv.org/
 [rocket-chip]: https://github.com/freechipsproject/rocket-chip
-[boom]: https://github.com/ucb-bar/riscv-boom
+[boom]: https://github.com/riscv-boom/riscv-boom
 [firemarshal]: https://github.com/firesim/FireMarshal/
 [ariane]: https://github.com/pulp-platform/ariane/
 [gemmini]: https://github.com/ucb-bar/gemmini

common.mk

@@ -104,7 +104,7 @@ $(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp
 	@echo "" > /dev/null
 
 firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
-	$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,-o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)) && touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
+	$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,-o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir) -ll $(FIRRTL_LOGLEVEL)) && touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
 # DOC include end: FirrtlCompiler
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
@@ -141,22 +141,44 @@ verilog: $(sim_vsrcs)
 #########################################################################################
 .PHONY: run-binary run-binary-fast run-binary-debug run-fast
 run-binary: $(output_dir) $(sim)
-	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
+	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
 
 #########################################################################################
 # helper rules to run simulator as fast as possible
 #########################################################################################
 run-binary-fast: $(output_dir) $(sim)
-	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) </dev/null | tee $(sim_out_name).log)
+	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null | tee $(sim_out_name).log)
 
 #########################################################################################
 # helper rules to run simulator with as much debug info as possible
 #########################################################################################
 run-binary-debug: $(output_dir) $(sim_debug)
-	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
+	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
 
 run-fast: run-asm-tests-fast run-bmark-tests-fast
 
+#########################################################################################
+# helper rules to run simulator with fast loadmem via hex files
+#########################################################################################
+$(binary_hex): $(output_dir) $(BINARY)
+	$(base_dir)/scripts/smartelf2hex.sh $(BINARY) > $(binary_hex)
+
+run-binary-hex: $(output_dir) $(sim) $(binary_hex)
+run-binary-hex: run-binary
+run-binary-hex: override LOADMEM_ADDR = 80000000
+run-binary-hex: override LOADMEM = $(binary_hex)
+run-binary-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR)
+run-binary-debug-hex: $(output_dir) $(sim) $(binary_hex)
+run-binary-debug-hex: run-binary-debug
+run-binary-debug-hex: override LOADMEM_ADDR = 80000000
+run-binary-debug-hex: override LOADMEM = $(binary_hex)
+run-binary-debug-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR)
+run-binary-fast-hex: $(output_dir) $(sim) $(binary_hex)
+run-binary-fast-hex: run-binary-fast
+run-binary-fast-hex: override LOADMEM_ADDR = 80000000
+run-binary-fast-hex: override LOADMEM = $(binary_hex)
+run-binary-fast-hex: override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR)
+
 #########################################################################################
 # run assembly/benchmarks rules
 #########################################################################################
@@ -167,10 +189,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% $(output_d
 	ln -sf $< $@
 
 $(output_dir)/%.run: $(output_dir)/% $(sim)
-	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@
+	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@
 
 $(output_dir)/%.out: $(output_dir)/% $(sim)
-	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
+	(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
 
 #########################################################################################
 # include build/project specific makefrags made from the generator

docs/Customization/Custom-Core.rst

@@ -0,0 +1,301 @@
+.. _custom_core:
+
+Adding a custom core
+====================
+
+You may want to integrate a custom RISC-V core into the Chipyard framework. This documentation page provides step-by-step
+instructions on how to achieve this.
+
+.. note:: 
+
+    RoCC is currently not supported by cores other than Rocket and BOOM. Please use Rocket or BOOM as the RoCC base core if you need to use RoCC.
+
+.. note::
+
+    This page contains links to the files that contains important definitions in the Rocket chip repository, which is maintained separately 
+    from Chipyard. If you find any discrepancy between the code on this page and the code in the source file, please report it through 
+    GitHub issues!
+
+Wrap Verilog Module with Blackbox (Optional)
+--------------------------------------------
+
+Since Chipyard uses Scala and Chisel, if the top module of your core is not in Chisel, you will first need to create a Verilog
+blackbox for it so that it can be processed by Chipyard. See :ref:`incorporating-verilog-blocks` for instructions.
+
+Create Parameter Case Classes
+-----------------------------
+
+Chipyard will generate a core for every ``InstantiableTileParams`` object it discovered in the ``TilesLocated(InSubsystem)`` key.
+This object is derived from``TileParams``, a trait containing the information needed to create a tile. All cores must have
+their own implementation of ``InstantiableTileParams``, as well as ``CoreParams`` which is passed as a field in ``TileParams``.
+
+``TileParams`` holds the parameters for the tile, which include parameters for all components in the tile (e.g.
+core, cache, MMU, etc.), while ``CoreParams`` contains parameters specific to the core on the tile. 
+They must be implemented as case classes with fields that can be overridden by 
+other config fragments as the constructor parameters. See the appendix at the bottom of the page for a list of 
+variable to be implemented. You can also add custom fields to them, but standard fields should always be preferred. 
+
+``InstantiableTileParams[TileType]`` holds the constructor of ``TileType`` on top of the fields of ``TileParams``, 
+where ``TileType`` is the tile class (see the next section).
+All custom cores will also need to implement ``instantiate()`` in their tile parameter class to return a new instance
+of the tile class ``TileType``. 
+
+``TileParams`` (in the file `BaseTile.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/BaseTile.scala>`_) ,
+``InstantiableTileParams`` (in the file `BaseTile.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/BaseTile.scala>`_),
+``CoreParams`` (in the file `Core.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Core.scala>`_),
+and ``FPUParams`` (in the file `FPU.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/FPU.scala>`_)
+contains the following fields:
+
+.. code-block:: scala
+
+    trait TileParams {
+      val core: CoreParams                  // Core parameters (see below)
+      val icache: Option[ICacheParams]      // Rocket specific: I1 cache option
+      val dcache: Option[DCacheParams]      // Rocket specific: D1 cache option
+      val btb: Option[BTBParams]            // Rocket specific: BTB / branch predictor option
+      val hartId: Int                       // Hart ID: Must be unique within a design config (This MUST be a case class parameter)
+      val beuAddr: Option[BigInt]           // Rocket specific: Bus Error Unit for Rocket Core
+      val blockerCtrlAddr: Option[BigInt]   // Rocket specific: Bus Blocker for Rocket Core
+      val name: Option[String]              // Name of the core
+    }
+
+    abstract class InstantiableTileParams[TileType <: BaseTile] extends TileParams {
+      def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)
+                    (implicit p: Parameters): TileType
+    }
+
+    trait CoreParams {
+      val bootFreqHz: BigInt              // Frequency
+      val useVM: Boolean                  // Support virtual memory
+      val useUser: Boolean                // Support user mode
+      val useSupervisor: Boolean          // Support supervisor mode
+      val useDebug: Boolean               // Support RISC-V debug specs
+      val useAtomics: Boolean             // Support A extension
+      val useAtomicsOnlyForIO: Boolean    // Support A extension for memory-mapped IO (may be true even if useAtomics is false)
+      val useCompressed: Boolean          // Support C extension
+      val useVector: Boolean = false      // Support V extension
+      val useSCIE: Boolean                // Support custom instructions (in custom-0 and custom-1)
+      val useRVE: Boolean                 // Use E base ISA
+      val mulDiv: Option[MulDivParams]    // *Rocket specific: M extension related setting (Use Some(MulDivParams()) to indicate M extension supported)
+      val fpu: Option[FPUParams]          // F and D extensions and related setting (see below)
+      val fetchWidth: Int                 // Max # of insts fetched every cycle
+      val decodeWidth: Int                // Max # of insts decoded every cycle
+      val retireWidth: Int                // Max # of insts retired every cycle
+      val instBits: Int                   // Instruction bits (if 32 bit and 64 bit are both supported, use 64)
+      val nLocalInterrupts: Int           // # of local interrupts (see SiFive interrupt cookbook)
+      val nPMPs: Int                      // # of Physical Memory Protection units
+      val pmpGranularity: Int             // Size of the smallest unit of region for PMP unit (must be power of 2)
+      val nBreakpoints: Int               // # of hardware breakpoints supported (in RISC-V debug specs)
+      val useBPWatch: Boolean             // Support hardware breakpoints
+      val nPerfCounters: Int              // # of supported performance counters
+      val haveBasicCounters: Boolean      // Support basic counters defined in the RISC-V counter extension 
+      val haveFSDirty: Boolean            // If true, the core will set FS field in mstatus CSR to dirty when appropriate
+      val misaWritable: Boolean           // Support writable misa CSR (like variable instruction bits)
+      val haveCFlush: Boolean             // Rocket specific: enables Rocket's custom instruction extension to flush the cache
+      val nL2TLBEntries: Int              // # of L2 TLB entries
+      val mtvecInit: Option[BigInt]       // mtvec CSR (of V extension) initial value
+      val mtvecWritable: Boolean          // If mtvec CSR is writable
+
+      // Normally, you don't need to change these values (except lrscCycles) 
+      def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs
+
+      def hasSupervisorMode: Boolean = useSupervisor || useVM
+      def instBytes: Int = instBits / 8
+      def fetchBytes: Int = fetchWidth * instBytes
+      // Rocket specific: Longest possible latency of Rocket core D1 cache. Simply set it to the default value 80 if you don't use it.
+      def lrscCycles: Int
+
+      def dcacheReqTagBits: Int = 6
+
+      def minFLen: Int = 32
+      def vLen: Int = 0
+      def sLen: Int = 0
+      def eLen(xLen: Int, fLen: Int): Int = xLen max fLen
+      def vMemDataBits: Int = 0
+    }
+ 
+    case class FPUParams(
+      minFLen: Int = 32,          // Minimum floating point length (no need to change) 
+      fLen: Int = 64,             // Maximum floating point length, use 32 if only single precision is supported
+      divSqrt: Boolean = true,    // Div/Sqrt operation supported
+      sfmaLatency: Int = 3,       // Rocket specific: Fused multiply-add pipeline latency (single precision)
+      dfmaLatency: Int = 4        // Rocket specific: Fused multiply-add pipeline latency (double precision)
+    )
+
+Most of the fields here (marked "Rocket spcific") are originally designed for the Rocket core and thus contain some 
+implementation-specific details, but many of them are general enough to be useful for other cores. You may ignore 
+any fields marked "Rocket specific" and use their default values; however, if you need to store additional information
+with meaning or usage similar to these "Rocket specific" fields, it is recommended to use these fields instead of 
+creating your own custom fields.
+
+You will also need a ``CanAttachTile`` class to add the tile config into the config system, with the following format:
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
+    :language: scala
+    :start-after: DOC include start: CanAttachTile
+    :end-before: DOC include end: CanAttachTile
+
+During elaboration, Chipyard will look for subclasses of ``CanAttachTile`` in the config system and instantiate a tile
+from the parameters in this class for every such class it found.
+
+.. note::
+
+    Implementations may choose to ignore some fields here or use them in a non-standard way, but using an inaccurate
+    value may break Chipyard components that rely on them (e.g. an inaccurate indication of supported ISA extension will
+    result in an incorrect test suite being generated) as well as any custom modules that use them. ALWAYS document any
+    fields you ignore or with altered usage in your core implementation, and if you are implementing other devices that
+    would look up these config values, also document them. "Rocket specific" values are generally safe to ignore, but 
+    you should document them if you use them.
+
+Create Tile Class
+-----------------
+
+In Chipyard, all Tiles are diplomatically instantiated. In the first phase, diplomatic nodes which specify Tile-to-System
+interconnects are evaluated, while in the second "Module Implementation" phase, hardware is elaborated. 
+See :ref:`tilelink_and_diplomacy` for more details. In this step, you will need to implement a tile class for your core,
+which specifies the constraints on the core's parameters and the connections with other diplomatic nodes. This class
+usually contains Diplomacy/TileLink code only, and Chisel RTL code should not go here.
+
+All tile classes implement ``BaseTile`` and will normally implement ``SinksExternalInterrupts`` and ``SourcesExternalNotifications``,
+which allow the tile to accept external interrupt. A typical tile has the following form:
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
+    :language: scala
+    :start-after: DOC include start: Tile class
+    :end-before: DOC include end: Tile class
+
+Connect TileLink Buses
+----------------------
+
+Chipyard uses TileLink as its onboard bus protocol. If your core doesn't use TileLink, you will need to insert converters 
+between the core's memory protocol and TileLink within the Tile module.
+in the tile class. Below is an example of how to connect a core using AXI4 to the TileLink bus with converters provided by
+Rocket chip: 
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
+    :language: scala
+    :start-after: DOC include start: AXI4 convert
+    :end-before: DOC include end: AXI4 convert
+
+Remember, you may not need all of these intermediate widgets. See :ref:`diplomatic_widgets` for the meaning of each intermediate
+widget. If you are using TileLink, then you only need the tap node and the TileLink node used by your components. Chipyard also
+provides converters for AHB, APB and AXIS, and most of the AXI4 widgets has equivalent widget for these bus protocol; see the 
+source files in ``generators/rocket-chip/src/main/scala/amba`` for more info. 
+
+If you are using some other bus protocol, you may implement your own converters, using the files in ``generators/rocket-chip/src/main/scala/amba``
+as the template, but it is not recommended unless you are familiar with TileLink. 
+
+``memAXI4Node`` is an AXI4 master node and is defined as following in our example:
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
+    :language: scala
+    :start-after: DOC include start: AXI4 node
+    :end-before: DOC include end: AXI4 node
+
+where ``portName`` and ``idBits`` (number of bits to represent a port ID) are the parameter provides by the tile.
+Make sure to read :ref:`node_types` to check out what type of nodes Chipyard supports and their parameters!
+
+Also, by default, there are boundary buffers for both master and slave connections to the bus when they are leaving the tile, and you
+can override the following two functions to control how to buffer the bus requests/responses:
+(You can find the definition of these two functions in the class ``BaseTile`` in the file
+`BaseTile.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/BaseTile.scala>`_)
+
+.. code-block:: scala
+
+    // By default, their value is "TLBuffer(BufferParams.none)".
+    protected def makeMasterBoundaryBuffers(implicit p: Parameters): TLBuffer
+    protected def makeSlaveBoundaryBuffers(implicit p: Parameters): TLBuffer
+
+You can find more information on ``TLBuffer`` in :ref:`diplomatic_widgets`.
+
+Create Implementation Class
+---------------------------
+
+The implementation class contains the parameterized, actual hardware that depends on the values resolved by the Diplomacy
+framework according to the info provided in the Tile class. This class will normally contains Chisel RTL code. If your
+core is in Verilog, you will need to instantiate the black box class that wraps your Verilog implementation and connect it with the buses
+and other components. No Diplomacy/TileLink code should be in this class; you should only connect the IO signals in TileLink
+interfaces or other diplomatically defined components, which are located in the tile class. 
+
+The implementation class for your core is of the following form:
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
+    :language: scala
+    :start-after: DOC include start: Implementation class
+    :end-before: DOC include end: Implementation class
+
+If you create an AXI4 node (or equivalents), you will need to connect them to your core. You can connect a port like this:
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
+    :language: scala
+    :start-after: DOC include start: AXI4 connect
+    :end-before: DOC include end: AXI4 connect
+
+Connect Interrupt
+-----------------
+
+Chipyard allows a tile to either receive interrupts from other devices or initiate interrupts to notify other cores/devices. 
+In the tile that inherited ``SinksExternalInterrupts``, one can create a ``TileInterrupts`` object (a Chisel bundle) and 
+call ``decodeCoreInterrupts()`` with the object as the argument. Note that you should call this function in the implementation
+class since it returns a Chisel bundle used by RTL code. You can then read the interrupt bits from the ``TileInterrupts`` bundle
+we create above. The definition of ``TileInterrupts`` 
+(in the file `Interrupts.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Interrupts.scala>`_) is 
+
+.. code-block:: scala
+
+    class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
+      val debug = Bool() // debug interrupt
+      val mtip = Bool() // Machine level timer interrupt
+      val msip = Bool() // Machine level software interrupt
+      val meip = Bool() // Machine level external interrupt 
+      val seip = usingSupervisor.option(Bool()) // Valid only if supervisor mode is supported
+      val lip = Vec(coreParams.nLocalInterrupts, Bool())  // Local interrupts
+    }
+
+Here is an example on how to connect these signals in the implementation class:
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
+    :language: scala
+    :start-after: DOC include start: connect interrupt
+    :end-before: DOC include end: connect interrupt
+
+Also, the tile can also notify other cores or devices for some events by calling following functions in ``SourcesExternalNotifications``
+from the implementation class:
+(These functions can be found in in the trait ``SourcesExternalNotifications`` in the file 
+`Interrupts.scala <https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/Interrupts.scala>`_)
+
+.. code-block:: scala
+
+    def reportHalt(could_halt: Option[Bool]) // Triggered when there is an unrecoverable hardware error (halt the machine)
+    def reportHalt(errors: Seq[CanHaveErrors]) // Varient for standard error bundle (Rocket specific: used only by cache when there's an ECC error)
+    def reportCease(could_cease: Option[Bool], quiescenceCycles: Int = 8) // Triggered when the core stop retiring instructions (like clock gating)
+    def reportWFI(could_wfi: Option[Bool]) // Triggered when a WFI instruction is executed
+
+Here is an example on how to use these functions to raise interrupt.
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
+    :language: scala
+    :start-after: DOC include start: raise interrupt
+    :end-before: DOC include end: raise interrupt
+
+Create Config Fragments to Integrate the Core
+---------------------------------------------
+
+To use your core in a Chipyard config, you will need a config fragment that will create a ``TileParams`` object of your core in
+the current config. An example of such config will be like this:
+
+.. literalinclude:: ../../generators/chipyard/src/main/scala/example/TutorialTile.scala
+    :language: scala
+    :start-after: DOC include start: Config fragment
+    :end-before: DOC include end: Config fragment
+
+Chipyard looks up the tile parameters in the field ``TilesLocated(InSubsystem)``, whose type is a list of ``InstantiableTileParams``.
+This config fragment simply appends new tile parameters to the end of this list. 
+
+Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions
+in :ref:`custom_chisel` to add your project to the build system, then create a config by following the steps in :ref:`hetero_socs_`.
+You can now run most desired workflows for the new config just as you would for the built-in cores (depending on the functionality your core supports). 
+
+If you would like to see an example of a complete third-party Verilog core integrated into Chipyard, ``generators/ariane/src/main/scala/ArianeTile.scala``
+provides a concrete example of the Ariane core. Note that this particular example includes additional nuances with respect to the interaction of the AXI
+interface with the memory coherency system. 

docs/Customization/Heterogeneous-SoCs.rst

@@ -1,3 +1,5 @@
+.. _hetero_socs_:
+
 Heterogeneous SoCs
 ===============================
 
@@ -8,7 +10,7 @@ Creating a Rocket and BOOM System
 -------------------------------------------
 
 Instantiating an SoC with Rocket and BOOM cores is all done with the configuration system and two specific config fragments.
-Both BOOM and Rocket have config fragments labelled ``WithNBoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_.
+Both BOOM and Rocket have config fragments labelled ``WithN{Small|Medium|Large|etc.}BoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_.
 When used together you can create a heterogeneous system.
 
 The following example shows a dual core BOOM with a single core Rocket.
@@ -18,52 +20,6 @@ The following example shows a dual core BOOM with a single core Rocket.
     :start-after: DOC include start: DualBoomAndRocket
     :end-before: DOC include end: DualBoomAndRocket
 
-In this example, the ``WithNBoomCores`` and ``WithNBigCores`` config fragments set up the default parameters for the multiple BOOM and Rocket cores, respectively.
-However, for BOOM, an extra config fragment called ``WithLargeBooms`` is added to override the default parameters with a different set of more common default parameters.
-This config fragment applies to all BOOM cores in the system and changes the parameters for each.
-
-Great! Now you have a heterogeneous setup with BOOMs and Rockets.
-The final thing you need to make this system work is to renumber the ``hartId``'s of the cores so that each core has a unique ``hartId`` (a ``hartId`` is the hardware thread id of the core).
-The ``WithRenumberHarts`` config fragment solves this by assigning a unique ``hartId`` to all cores in the system (it can label the Rocket cores first or the BOOM cores first).
-The reason this is needed is because by default the ``WithN...Cores(X)`` config fragment assumes that there are only BOOM or only Rocket cores in the system.
-Thus, without the ``WithRenumberHarts`` config fragment, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``.
-
-Another alternative option to create a multi heterogeneous core system is to override the parameters yourself so you can specify the core parameters per core.
-The config fragment to add to your system would look something like the following.
-
-.. code-block:: scala
-
-    // create 6 cores (4 boom and 2 rocket)
-    class WithHeterCoresSetup extends Config((site, here, up) => {
-      case BoomTilesKey => {
-        val boomTile0 = BoomTileParams(...) // params for boom core 0
-        val boomTile1 = BoomTileParams(...) // params for boom core 1
-        val boomTile2 = BoomTileParams(...) // params for boom core 2
-        val boomTile3 = BoomTileParams(...) // params for boom core 3
-        Seq(boomTile0, boomTile1, boomTile2, boomTile3)
-      }
-
-      case RocketTilesKey => {
-        val rocketTile0 = RocketTileParams(...) // params for rocket core 0
-        val rocketTile1 = RocketTileParams(...) // params for rocket core 1
-        Seq(rocketTile0, rocketTile1)
-      }
-    })
-
-Then you could use this new config fragment like the following.
-
-.. code-block:: scala
-
-    class SixCoreConfig extends Config(
-      new WithTSI ++
-      new WithBootROM ++
-      new WithUART ++
-      new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-      new freechips.rocketchip.subsystem.WithNoSlavePort ++
-      new WithHeterCoresSetup ++
-      new freechips.rocketchip.system.BaseConfig)
-
-Note, in this setup you need to specify the ``hartId`` of each core in the "TileParams", where each ``hartId`` is unique.
 
 Adding Hwachas
 -------------------------------------------
@@ -92,8 +48,7 @@ An example is shown below with two BOOM cores, and one Rocket tile with a RoCC a
     :start-after: DOC include start: DualBoomAndRocketOneHwacha
     :end-before: DOC include end: DualBoomAndRocketOneHwacha
 
-In this example, the ``WithRenumberHarts`` relabels the ``hartId``'s of all the BOOM/Rocket cores.
+The ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core).
-Then after that is applied to the parameters, the ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core).
 Finally, the ``WithMultiRoCC`` config fragment is called.
 This config fragment sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default.
 This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter.

docs/Customization/index.rst

@@ -7,6 +7,8 @@ These guides will walk you through customization of your system-on-chip:
 
 - How to include your custom Chisel sources in the Chipyard build system
 
+- Adding custom core
+
 - Adding custom RoCC accelerators to an existing Chipyard core (BOOM or Rocket)
 
 - Adding custom MMIO widgets to the Chipyard memory system by Tilelink or AXI4, with custom Top-level IOs
@@ -35,6 +37,7 @@ We recommend reading all these pages in order. Hit next to get started!
 
    Heterogeneous-SoCs
    Custom-Chisel
+   Custom-Core
    RoCC-or-MMIO
    RoCC-Accelerators
    MMIO-Peripherals

docs/Simulation/Software-RTL-Simulation.rst

@@ -62,6 +62,12 @@ For instance, to run one of the riscv-tools assembly tests.
 
 .. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``.
 
+The makefiles have a ``run-binary`` rule that simplifies running the simulation executable. It adds many of the common command line options for you and redirects the output to a file.
+
+.. code-block:: shell
+
+    make run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+
 Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``.
 For example:
 
@@ -126,6 +132,29 @@ All ``make`` targets that can be applied to the default example, can also be app
 Finally, in the ``generated-src/<...>-<package>-<config>/`` directory resides all of the collateral and Verilog source files for the build/simulation.
 Specifically, the SoC top-level (``TOP``) Verilog file is denoted with ``*.top.v`` while the ``TestHarness`` file is denoted with ``*.harness.v``.
 
+Fast Memory Loading
+-------------------
+
+The simulator loads the program binary over a simulated serial line. This can be quite slow if there is a lot of static data, so the simulator also allows data to be loaded from a file directly into the DRAM model.
+
+.. code-block:: shell
+
+    make run-binary BINARY=test.riscv LOADMEM=testdata.hex LOADMEM_ADDR=81000000
+
+The ``.hex`` file should be a text file with a hexadecimal number on each line.
+
+.. code-block:: text
+
+    deadbeef
+    0123
+
+Each line uses little-endian order, so this file would produce the bytes "ef be ad de 01 23". ``LOADMEM_ADDR`` specifies which address in memory (in hexadecimal) to write the first byte to. The default is 0x81000000.
+
+A special target that facilitates automatically generating a hex file for an entire elf RISC-V exectuable and then running the simulator with the appropriate flags is also available.
+
+.. code-block:: shell
+
+    make run-binary-hex BINARY=test.riscv
 
 Generating Waveforms
 -----------------------

docs/TileLink-Diplomacy-Reference/NodeTypes.rst

@@ -1,3 +1,5 @@
+.. _node_types:
+
 TileLink Node Types
 ===================
 

docs/TileLink-Diplomacy-Reference/Widgets.rst

@@ -1,3 +1,5 @@
+.. _diplomatic_widgets:
+
 Diplomatic Widgets
 ==================
 

docs/TileLink-Diplomacy-Reference/index.rst

@@ -1,3 +1,5 @@
+.. _tilelink_and_diplomacy:
+
 TileLink and Diplomacy Reference
 ================================
 

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -25,7 +25,7 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
 
-import chipyard.{BuildTop, BuildSystem}
+import chipyard.{BuildTop, BuildSystem, TestSuitesKey, TestSuiteHelper}
 
 /**
  * TODO: Why do we need this?
@@ -51,9 +51,9 @@ class WithGPIO extends Config((site, here, up) => {
 })
 // DOC include end: gpio config fragment
 
-class WithUART extends Config((site, here, up) => {
+class WithUART(baudrate: BigInt = 115200) extends Config((site, here, up) => {
   case PeripheryUARTKey => Seq(
-    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256))
+    UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256, initBaudRate = baudrate))
 })
 
 class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => {
@@ -99,16 +99,18 @@ class WithMultiRoCC extends Config((site, here, up) => {
  *
  * @param harts harts to specify which will get a Hwacha
  */
-class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
+class WithMultiRoCCHwacha(harts: Int*) extends Config(
-  case MultiRoCCKey => {
+  new chipyard.config.WithHwachaTest ++
-    up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
+  new Config((site, here, up) => {
-      (i -> Seq((p: Parameters) => {
+    case MultiRoCCKey => {
-        LazyModule(new Hwacha()(p)).suggestName("hwacha")
+      up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
-      }))
+        (i -> Seq((p: Parameters) => {
+          LazyModule(new Hwacha()(p)).suggestName("hwacha")
+        }))
+      }
     }
-  }
+  })
-})
+)
-
 
 class WithTraceIO extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
@@ -130,3 +132,27 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
     case other => other
   }
 })
+
+class WithRocketICacheScratchpad extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x100000 + r.hartId * 0x10000))))
+  }
+})
+
+class WithRocketDCacheScratchpad extends Config((site, here, up) => {
+  case RocketTilesKey => up(RocketTilesKey, site) map { r =>
+    r.copy(dcache = r.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + r.hartId * 0x10000))))
+  }
+})
+
+class WithHwachaTest extends Config((site, here, up) => {
+  case TestSuitesKey => (tileParams: Seq[TileParams], suiteHelper: TestSuiteHelper, p: Parameters) => {
+    up(TestSuitesKey).apply(tileParams, suiteHelper, p)
+    import hwacha.HwachaTestSuites._
+    suiteHelper.addSuites(rv64uv.map(_("p")))
+    suiteHelper.addSuites(rv64uv.map(_("vp")))
+    suiteHelper.addSuite(rv64sv("p"))
+    suiteHelper.addSuite(hwachaBmarks)
+    "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha"
+  }
+})

generators/chipyard/src/main/scala/IOBinders.scala

@@ -5,11 +5,11 @@ import chisel3._
 import chisel3.experimental.{Analog, IO}
 
 import freechips.rocketchip.config.{Field, Config, Parameters}
-import freechips.rocketchip.diplomacy.{LazyModule}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.{SimAXIMem}
-import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters}
+import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
 import freechips.rocketchip.util._
 import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
 
@@ -52,6 +52,21 @@ case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]](
   Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil)
 )
 
+// Note: The parameters instance is accessible only through LazyModule
+// or LazyModuleImpLike. The self-type requirement in traits like
+// CanHaveMasterAXI4MemPort is insufficient to make it accessible to the IOBinder
+// As a result, IOBinders only work on Modules which inherit LazyModule or
+// or LazyModuleImpLike
+object GetSystemParameters {
+  def apply(s: Any): Parameters = {
+    s match {
+      case s: LazyModule => s.p
+      case s: LazyModuleImpLike => s.p
+      case _ => throw new Exception(s"Trying to get Parameters from a system that is not LazyModule or LazyModuleImpLike")
+    }
+  }
+}
+
 // This macro overrides previous matches on some Top mixin. This is useful for
 // binders which drive IO, since those typically cannot be composed
 class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
@@ -185,10 +200,19 @@ object AddIOCells {
     (port, ios)
   }
 
-  def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = {
+  def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = {
     io.zip(node.in).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => {
-      val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_mem_axi4_${i}"))
+      val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_slave_${i}"))
-      port.suggestName(s"mem_axi4_${i}")
+      port.suggestName(s"${name}_axi4_slave_${i}")
+      (port, edge, ios)
+    }}
+  }
+  def axi4(io: Seq[AXI4Bundle], node: AXI4MasterNode, name: String): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = {
+    io.zip(node.out).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => {
+      //val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_${name}_axi4_master_${i}"))
+      val port = IO(Flipped(AXI4Bundle(edge.bundle)))
+      val ios = IOCell.generateFromSignal(mem_axi4, port, Some(s"iocell_${name}_axi4_master_${i}"))
+      port.suggestName(s"${name}_axi4_master_${i}")
       (port, edge, ios)
     }}
   }
@@ -256,22 +280,19 @@ class WithSimNIC extends OverrideIOBinder({
   (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil
 })
 
-// Note: The parameters instance is accessible only through the BaseSubsystem
-// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The
-// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it
-// accessible to the IOBinder
 // DOC include start: WithSimAXIMem
 class WithSimAXIMem extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
+  (system: CanHaveMasterAXI4MemPort) => {
-    val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node)
+    implicit val p: Parameters = GetSystemParameters(system)
+    val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem")
     // TODO: we are inlining the connectMem method of SimAXIMem because
     //   it takes in a dut rather than seq of axi4 ports
     val harnessFn = (th: chipyard.TestHarness) => {
       peiTuples.map { case (port, edge, ios) =>
-        val mem = LazyModule(new SimAXIMem(edge, size = system.p(ExtMem).get.master.size)(system.p))
+        val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size))
         Module(mem.module).suggestName("mem")
         mem.io_axi4.head <> port
-        }
+      }
       Nil
     }
     Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn)))
@@ -280,12 +301,13 @@ class WithSimAXIMem extends OverrideIOBinder({
 // DOC include end: WithSimAXIMem
 
 class WithBlackBoxSimMem extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
+  (system: CanHaveMasterAXI4MemPort) => {
-    val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node)
+    implicit val p: Parameters = GetSystemParameters(system)
+    val peiTuples = AddIOCells.axi4(system.mem_axi4, system.memAXI4Node, "mem")
     val harnessFn = (th: chipyard.TestHarness) => {
       peiTuples.map { case (port, edge, ios) =>
-        val memSize = system.p(ExtMem).get.master.size
+        val memSize = p(ExtMem).get.master.size
-        val lineSize = system.p(CacheBlockBytes)
+        val lineSize = p(CacheBlockBytes)
         val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle))
         mem.io.axi <> port
         mem.io.clock := th.clock
@@ -298,7 +320,19 @@ class WithBlackBoxSimMem extends OverrideIOBinder({
 })
 
 class WithSimAXIMMIO extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MMIOPort with BaseSubsystem) => SimAXIMem.connectMMIO(system)(system.p); Nil
+  (system: CanHaveMasterAXI4MMIOPort) => {
+    implicit val p: Parameters = GetSystemParameters(system)
+    val peiTuples = AddIOCells.axi4(system.mmio_axi4, system.mmioAXI4Node, "mmio_mem")
+    val harnessFn = (th: chipyard.TestHarness) => {
+      peiTuples.zipWithIndex.map { case ((port, edge, ios), i) =>
+        val mmio_mem = LazyModule(new SimAXIMem(edge, size = 4096))
+        Module(mmio_mem.module).suggestName(s"mmio_mem_${i}")
+        mmio_mem.io_axi4.head <> port
+      }
+      Nil
+    }
+    Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn)))
+  }
 })
 
 class WithDontTouchPorts extends OverrideIOBinder({
@@ -315,21 +349,16 @@ class WithTieOffInterrupts extends OverrideIOBinder({
 })
 
 class WithTieOffL2FBusAXI extends OverrideIOBinder({
-  (system: CanHaveSlaveAXI4Port with BaseSubsystem) => {
+  (system: CanHaveSlaveAXI4Port) => {
-    system.l2_frontend_bus_axi4.foreach(axi => {
+    val peiTuples = AddIOCells.axi4(system.l2_frontend_bus_axi4, system.l2FrontendAXI4Node, "l2_fbus")
-      axi.tieoff()
+    val harnessFn = (th: chipyard.TestHarness) => {
-      experimental.DataMirror.directionOf(axi.ar.ready) match {
+      peiTuples.zipWithIndex.map { case ((port, edge, ios), i) =>
-        case ActualDirection.Input =>
+        port := DontCare // tieoff doesn't completely tie-off, for some reason
-          axi.r.bits := DontCare
+        port.tieoff()
-          axi.b.bits := DontCare
-        case ActualDirection.Output =>
-          axi.aw.bits := DontCare
-          axi.ar.bits := DontCare
-          axi.w.bits := DontCare
-        case _ => throw new Exception("Unknown AXI port direction")
       }
-    })
+      Nil
-    Nil
+    }
+    Seq((peiTuples.map(_._1), peiTuples.flatMap(_._3), Some(harnessFn)))
   }
 })
 

generators/chipyard/src/main/scala/TestSuites.scala

@@ -3,8 +3,8 @@ package chipyard
 import scala.collection.mutable.{LinkedHashSet}
 
 import freechips.rocketchip.subsystem._
-import freechips.rocketchip.tile.{XLen}
+import freechips.rocketchip.tile.{XLen, TileParams}
-import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
 import boom.common.{BoomTileAttachParams}
@@ -64,133 +64,51 @@ class TestSuiteHelper
   def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
 
   /**
-  * Add BOOM tests (asm, bmark, regression)
+  * Add generic tests (asm, bmark, regression) for all cores.
   */
-  def addBoomTestSuites(implicit p: Parameters) = {
+  def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = {
     val xlen = p(XLen)
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
+    tiles.find(_.hartId == 0).map { tileParams =>
-      case tp: BoomTileAttachParams => {
+      val coreParams = tileParams.core
-        val tileParams = tp.tileParams
+      val vm = coreParams.useVM
-        val coreParams = tileParams.core
+      val env = if (vm) List("p","v") else List("p")
-        val vm = coreParams.useVM
+      coreParams.fpu foreach { case cfg =>
-        val env = if (vm) List("p","v") else List("p")
+        if (xlen == 32) {
-        coreParams.fpu foreach { case cfg =>
+          addSuites(env.map(rv32uf))
-          if (xlen == 32) {
+          if (cfg.fLen >= 64)
-            addSuites(env.map(rv32uf))
+            addSuites(env.map(rv32ud))
-            if (cfg.fLen >= 64) {
+        } else {
-              addSuites(env.map(rv32ud))
+          addSuite(rv32udBenchmarks)
-            }
+          addSuites(env.map(rv64uf))
-          } else if (cfg.fLen >= 64) {
+          if (cfg.fLen >= 64)
             addSuites(env.map(rv64ud))
-            addSuites(env.map(rv64uf))
-            addSuite(rv32udBenchmarks)
-          }
         }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          } else {
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-          }
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites(rvu.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
       }
-      case _ =>
+      if (coreParams.useAtomics) {
-    }
+        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-  }
+          addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-
+        else
-  /**
+          addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-  * Add Rocket tests (asm, bmark, regression)
-  */
-  def addRocketTestSuites(implicit p: Parameters) = {
-    val xlen = p(XLen)
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
-      case tp: RocketTileAttachParams => {
-        val tileParams = tp.tileParams
-        val coreParams = tileParams.core
-        val vm = coreParams.useVM
-        val env = if (vm) List("p","v") else List("p")
-        coreParams.fpu foreach { case cfg =>
-          if (xlen == 32) {
-            addSuites(env.map(rv32uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv32ud))
-          } else {
-            addSuite(rv32udBenchmarks)
-            addSuites(env.map(rv64uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv64ud))
-          }
-        }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          else
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
       }
-      case _ =>
+      if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-    }
+      val (rvi, rvu) =
-  }
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        else            ((if (vm) rv32i else rv32pi), rv32u)
 
-  /**
+      addSuites(rvi.map(_("p")))
-  * Add Ariane tests (asm, bmark, regression)
+      addSuites(rvu.map(_("p")))
-  */
+      addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-  def addArianeTestSuites(implicit p: Parameters) = {
+      addSuite(benchmarks)
-    val xlen = p(XLen)
+      addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
-    p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
-      case tp: ArianeTileAttachParams => {
-        val tileParams = tp.tileParams
-        val coreParams = tileParams.core
-        val vm = coreParams.useVM
-        val env = if (vm) List("p","v") else List("p")
-        coreParams.fpu foreach { case cfg =>
-          if (xlen == 32) {
-            addSuites(env.map(rv32uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv32ud))
-          } else {
-            addSuite(rv32udBenchmarks)
-            addSuites(env.map(rv64uf))
-            if (cfg.fLen >= 64)
-              addSuites(env.map(rv64ud))
-          }
-        }
-        if (coreParams.useAtomics) {
-          if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-            addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-          else
-            addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-        }
-        if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-        val (rvi, rvu) =
-          if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-          else            ((if (vm) rv32i else rv32pi), rv32u)
-
-        addSuites(rvi.map(_("p")))
-        addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-        addSuite(benchmarks)
-        addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
-      }
-      case _ =>
     }
   }
 }
+
+/**
+ * Config key of custom test suite.
+ */
+case object TestSuitesKey extends Field[(Seq[TileParams], TestSuiteHelper, Parameters) => String]((tiles, helper, p) => {
+  helper.addGenericTestSuites(tiles)(p)
+  // Return an empty string as makefile additional snippets
+  ""
+})

generators/chipyard/src/main/scala/config/AbstractConfig.scala

@@ -0,0 +1,26 @@
+package chipyard.config
+
+import freechips.rocketchip.config.{Config}
+
+// --------------
+// Chipyard abstract ("base") configuration
+// NOTE: This configuration is NOT INSTANTIABLE, as it defines a empty system with no tiles
+// --------------
+
+class AbstractConfig extends Config(
+  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a blackbox DRAMSim model
+  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
+  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
+  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
+  new chipyard.config.WithBootROM ++                             // use default bootrom
+  new chipyard.config.WithUART ++                                // add a UART
+  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
+  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
+

generators/chipyard/src/main/scala/config/ArianeConfigs.scala

@@ -9,34 +9,11 @@ import freechips.rocketchip.config.{Config}
 // ---------------------
 
 class ArianeConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
+  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithSimAXIMem ++                        // drive the master AXI4 memory with a SimAXIMem
-  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
-  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
-  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithBootROM ++                             // use default bootrom
-  new chipyard.config.WithUART ++                                // add a UART
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
-  new ariane.WithNArianeCores(1) ++                              // single Ariane core
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
-  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
 
 class dmiArianeConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTiedOffSerial ++          // Tie off the serial port, override default instantiation of SimSerial
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation, override default tie-off debug
-  new chipyard.iobinders.WithSimAXIMem ++
+  new ariane.WithNArianeCores(1) ++                    // single Ariane core
-  new chipyard.iobinders.WithTiedOffSerial ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new ariane.WithNArianeCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)

generators/chipyard/src/main/scala/config/BoomConfigs.scala

@@ -7,151 +7,39 @@ import freechips.rocketchip.config.{Config}
 // ---------------------
 
 class SmallBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
-  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
-  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a SimAXIMem
-  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
-  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
-  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithBootROM ++                             // use default bootrom
-  new chipyard.config.WithUART ++                                // add a UART
-  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
   new boom.common.WithNSmallBooms(1) ++                          // small boom config
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
 
 class MediumBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new boom.common.WithNMediumBooms(1) ++                         // medium boom config
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new boom.common.WithNMediumBooms(1) ++                             // medium boom config
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 
 class LargeBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new boom.common.WithNLargeBooms(1) ++                          // large boom config
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class MegaBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new boom.common.WithNMegaBooms(1) ++                           // mega boom config
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new boom.common.WithNMegaBooms(1) ++                        // mega boom config
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 
 class DualSmallBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new boom.common.WithNSmallBooms(2) ++                          // 2 boom cores
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new boom.common.WithNSmallBooms(2) ++                         // 2 boom cores
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 
 class HwachaLargeBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.config.WithHwachaTest ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new hwacha.DefaultHwachaConfig ++                         // use Hwacha vector accelerator
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new boom.common.WithNLargeBooms(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class LoopbackNICLargeBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithLoopbackNIC ++                      // drive NIC IOs with loopback
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new icenet.WithIceNIC ++                                       // build a NIC
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new chipyard.iobinders.WithLoopbackNIC ++                        // drive NIC IOs with loopback
-  new testchipip.WithTSI ++
-  new icenet.WithIceNIC ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new boom.common.WithNLargeBooms(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class DromajoBoomConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithSimDromajoBridge ++                 // attach Dromajo
-  new testchipip.WithTSI ++
   new chipyard.config.WithTraceIO ++                             // enable the traceio
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new boom.common.WithNSmallBooms(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
-

generators/chipyard/src/main/scala/config/HeteroConfigs.scala

@@ -7,108 +7,39 @@ import freechips.rocketchip.config.{Config}
 // ---------------------
 
 class LargeBoomAndRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
-  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
-  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a SimAXIMem
-  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
-  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
-  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithBootROM ++                             // use default bootrom
-  new chipyard.config.WithUART ++                                // add a UART
-  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
   new boom.common.WithNLargeBooms(1) ++                          // single-core boom
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
 
 // DOC include start: BoomAndRocketWithHwacha
 class HwachaLargeBoomAndHwachaRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.config.WithHwachaTest ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new hwacha.DefaultHwachaConfig ++                          // add hwacha to all harts
-  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new boom.common.WithNLargeBooms(1) ++                      // add 1 boom core
-  new chipyard.iobinders.WithTiedOffDebug ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++     // add 1 rocket core
-  new chipyard.iobinders.WithSimSerial ++
+  new chipyard.config.AbstractConfig)
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new hwacha.DefaultHwachaConfig ++                      // add hwacha to all harts
-  new boom.common.WithNLargeBooms(1) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: BoomAndRocketWithHwacha
-// DOC include start: DualBoomAndRocketOneHwacha
 
+// DOC include start: DualBoomAndRocketOneHwacha
 class LargeBoomAndHwachaRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
   new chipyard.config.WithMultiRoCC ++                                  // support heterogeneous rocc
   new chipyard.config.WithMultiRoCCHwacha(1) ++                         // put hwacha on hart-1 (rocket)
-  new chipyard.config.WithL2TLBs(1024) ++
+  new hwacha.DefaultHwachaConfig ++                                     // set default hwacha config keys
-  new boom.common.WithNLargeBooms(1) ++
+  new boom.common.WithNLargeBooms(1) ++                                 // add 1 boom core
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++                // add 1 rocket core
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: DualBoomAndRocketOneHwacha
 
 
 // DOC include start: DualBoomAndRocket
 class DualLargeBoomAndDualRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new boom.common.WithNLargeBooms(2) ++                   // add 2 boom cores
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new freechips.rocketchip.subsystem.WithNBigCores(2) ++  // add 2 rocket cores
-  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new boom.common.WithNLargeBooms(2) ++                   // 2 boom cores
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(2) ++   // 2 rocket cores
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: DualBoomAndRocket
 
 class LargeBoomAndRocketWithControlCoreConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small "control" core
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new boom.common.WithNLargeBooms(1) ++                    // Add 1 boom core
-  new chipyard.iobinders.WithBlackBoxSimMem ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // add 1 rocket core
-  new chipyard.iobinders.WithTiedOffDebug ++
+  new chipyard.config.AbstractConfig)
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small control core
-  new boom.common.WithNLargeBooms(1) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
-

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -7,538 +7,180 @@ import freechips.rocketchip.config.{Config}
 // --------------
 
 class RocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++                      // display UART with a SimUARTAdapter
-  new chipyard.iobinders.WithTieOffInterrupts ++                 // tie off top-level interrupts
-  new chipyard.iobinders.WithBlackBoxSimMem ++                   // drive the master AXI4 memory with a blackbox DRAMSim model
-  new chipyard.iobinders.WithTiedOffDebug ++                     // tie off debug (since we are using SimSerial for testing)
-  new chipyard.iobinders.WithSimSerial ++                        // drive TSI with SimSerial for testing
-  new testchipip.WithTSI ++                                      // use testchipip serial offchip link
-  new chipyard.config.WithBootROM ++                             // use default bootrom
-  new chipyard.config.WithUART ++                                // add a UART
-  new chipyard.config.WithL2TLBs(1024) ++                        // use L2 TLBs
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++           // no top-level MMIO master port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++       // use Sifive L2 cache
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++  // hierarchical buses including mbus+l2
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)                    // "base" rocketchip system
 
 class HwachaRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.config.WithHwachaTest ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new hwacha.DefaultHwachaConfig ++                        // use Hwacha vector accelerator
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 // DOC include start: GemminiRocketConfig
 class GemminiRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new gemmini.DefaultGemminiConfig ++                        // use Gemmini systolic array GEMM accelerator
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GemminiRocketConfig
 
-class RoccRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithRoccExample ++    // use example RoCC-based accelerator
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
-
 // DOC include start: JtagRocket
 class jtagRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithSimDebug ++                   // add SimDebug, in addition to default SimSerial
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithSimDebug ++    // add SimJtag and SimSerial, use both to drive sim
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new freechips.rocketchip.subsystem.WithJtagDTM ++        // sets DTM communication interface to JTAG
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: JtagRocket
 
 // DOC include start: DmiRocket
 class dmiRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithTiedOffSerial ++          // tie-off serial, override default add SimSerial
-  new chipyard.iobinders.WithTieOffInterrupts ++
+  new chipyard.iobinders.WithSimDebug ++               // add SimDebug, override default tie-off debug
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffSerial ++
-  new chipyard.iobinders.WithSimDebug ++               // add SimDebug and use it to drive simulation
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: DmiRocket
 
 // DOC include start: GCDTLRocketConfig
 class GCDTLRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++          // Use GCD Chisel, connect Tilelink
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GCDTLRocketConfig
 
 // DOC include start: GCDAXI4BlackBoxRocketConfig
 class GCDAXI4BlackBoxRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++          // Use GCD blackboxed verilog, connect by AXI4->Tilelink
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GCDAXI4BlackBoxRocketConfig
 
 class LargeSPIFlashROMRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithSimSPIFlashModel(true) ++      // add the SPI flash model in the harness (read-only)
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
   new chipyard.config.WithSPIFlash ++                       // add the SPI flash controller
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class SmallSPIFlashRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithSimSPIFlashModel(false) ++     // add the SPI flash model in the harness (writeable)
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
   new chipyard.config.WithSPIFlash(0x100000) ++             // add the SPI flash controller (1 MiB)
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class SimAXIRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
+  new chipyard.iobinders.WithSimAXIMem ++                   // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithSimAXIMem ++                       // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class SimBlockDeviceRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithSimBlockDevice ++             // drive block-device IOs with SimBlockDevice
-  new testchipip.WithTSI ++
   new testchipip.WithBlockDevice ++                        // add block-device module to peripherybus
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class BlockDeviceModelRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithBlockDeviceModel ++           // drive block-device IOs with a BlockDeviceModel
-  new testchipip.WithTSI ++
   new testchipip.WithBlockDevice ++                        // add block-device module to periphery bus
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 // DOC include start: GPIORocketConfig
 class GPIORocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithGPIOTiedOff ++                // tie off GPIO inputs into the top
-  new testchipip.WithTSI ++
   new chipyard.config.WithGPIO ++                          // add GPIOs to the peripherybus
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: GPIORocketConfig
 
 class QuadRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(4) ++   // quad-core (4 RocketTiles)
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class RV32RocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
   new freechips.rocketchip.subsystem.WithRV32 ++           // set RocketTiles to be 32-bit
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class GB1MemoryRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 // DOC include start: Sha3Rocket
 class Sha3RocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: Sha3Rocket
 
 // DOC include start: InitZeroRocketConfig
 class InitZeroRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++                // add InitZero
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: InitZeroRocketConfig
 
 class LoopbackNICRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
   new chipyard.iobinders.WithLoopbackNIC ++                        // drive NIC IOs with loopback
-  new testchipip.WithTSI ++
   new icenet.WithIceNIC ++                                         // add an IceNIC
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 // DOC include start: l1scratchpadrocket
-class L1ScratchpadSmallRocketConfig extends Config(
+class ScratchpadOnlyRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use rocket l1 DCache scratchpad as base phys mem
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use rocket l1 scratchpad
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: l1scratchpadrocket
 
+class L1ScratchpadRocketConfig extends Config(
+  new chipyard.config.WithRocketICacheScratchpad ++   // use rocket ICache scratchpad
+  new chipyard.config.WithRocketDCacheScratchpad ++   // use rocket DCache scratchpad
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
 // DOC include start: mbusscratchpadrocket
 class MbusScratchpadRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
   new testchipip.WithBackingScratchpad ++                   // add mbus backing scratchpad
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++       // remove offchip mem port
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: mbusscratchpadrocket
 
 // DOC include start: RingSystemBusRocket
 class RingSystemBusRocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new testchipip.WithRingSystemBus ++ // Ring-topology system bus
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: RingSystemBusRocket
 
 class StreamingPassthroughRocketConfig extends Config(
   new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled streaming passthrough
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 // DOC include start: StreamingFIRRocketConfig
 class StreamingFIRRocketConfig extends Config (
   new chipyard.example.WithStreamingFIR ++ // use top with tilelink-controlled streaming FIR
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 // DOC include end: StreamingFIRRocketConfig
 
 class SmallNVDLARocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
 
 class LargeNVDLARocketConfig extends Config(
-  new chipyard.iobinders.WithUARTAdapter ++
-  new chipyard.iobinders.WithTieOffInterrupts ++
-  new chipyard.iobinders.WithBlackBoxSimMem ++
-  new chipyard.iobinders.WithTiedOffDebug ++
-  new chipyard.iobinders.WithSimSerial ++
-  new testchipip.WithTSI ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithUART ++
-  new chipyard.config.WithL2TLBs(1024) ++
   new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new chipyard.config.AbstractConfig)
-  new freechips.rocketchip.system.BaseConfig)
+
+class MMIORocketConfig extends Config(
+  new chipyard.iobinders.WithTieOffL2FBusAXI ++ // Tie-off the incoming MMIO port
+  new chipyard.iobinders.WithSimAXIMMIO ++ // Attach a simulated memory to the outwards MMIO port
+  new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
+  new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -0,0 +1,236 @@
+package chipyard.example
+
+import chisel3._
+import chisel3.util._
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalTreeNode}
+import freechips.rocketchip.rocket._
+import freechips.rocketchip.subsystem.{RocketCrossingParams}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
+import freechips.rocketchip.util._
+import freechips.rocketchip.tile._
+import freechips.rocketchip.amba.axi4._
+
+// Example parameter class copied from Ariane, not included in documentation but for compile check only
+// If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
+// out what parameters you need before you write the parameter class
+case class MyCoreParams(
+  bootFreqHz: BigInt = BigInt(1700000000),
+  rasEntries: Int = 4,
+  btbEntries: Int = 16,
+  bhtEntries: Int = 16,
+  enableToFromHostCaching: Boolean = false,
+) extends CoreParams {
+  val useVM: Boolean = true
+  val useUser: Boolean = true
+  val useSupervisor: Boolean = false
+  val useDebug: Boolean = true
+  val useAtomics: Boolean = true
+  val useAtomicsOnlyForIO: Boolean = false // copied from Rocket
+  val useCompressed: Boolean = true
+  override val useVector: Boolean = false
+  val useSCIE: Boolean = false
+  val useRVE: Boolean = false
+  val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket
+  val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket
+  val nLocalInterrupts: Int = 0
+  val nPMPs: Int = 0 // TODO: Check
+  val pmpGranularity: Int = 4 // copied from Rocket
+  val nBreakpoints: Int = 0 // TODO: Check
+  val useBPWatch: Boolean = false
+  val nPerfCounters: Int = 29
+  val haveBasicCounters: Boolean = true
+  val haveFSDirty: Boolean = false
+  val misaWritable: Boolean = false
+  val haveCFlush: Boolean = false
+  val nL2TLBEntries: Int = 512 // copied from Rocket
+  val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket
+  val mtvecWritable: Boolean = true // copied from Rocket
+  val instBits: Int = if (useCompressed) 16 else 32
+  val lrscCycles: Int = 80 // copied from Rocket
+  val decodeWidth: Int = 1 // TODO: Check
+  val fetchWidth: Int = 1 // TODO: Check
+  val retireWidth: Int = 2
+}
+
+// DOC include start: CanAttachTile
+case class MyTileAttachParams(
+  tileParams: MyTileParams,
+  crossingParams: RocketCrossingParams
+) extends CanAttachTile {
+  type TileType = MyTile
+  val lookup = PriorityMuxHartIdFromSeq(Seq(tileParams))
+}
+// DOC include end: CanAttachTile
+
+case class MyTileParams(
+  name: Option[String] = Some("my_tile"),
+  hartId: Int = 0,
+  trace: Boolean = false,
+  val core: MyCoreParams = MyCoreParams()
+) extends InstantiableTileParams[MyTile]
+{
+  val beuAddr: Option[BigInt] = None
+  val blockerCtrlAddr: Option[BigInt] = None
+  val btb: Option[BTBParams] = Some(BTBParams())
+  val boundaryBuffers: Boolean = false
+  val dcache: Option[DCacheParams] = Some(DCacheParams())
+  val icache: Option[ICacheParams] = Some(ICacheParams())
+  def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
+    new MyTile(this, crossing, lookup)
+  }
+}
+
+// DOC include start: Tile class
+class MyTile(
+  val myParams: MyTileParams,
+  crossing: ClockCrossingType,
+  lookup: LookupByHartIdImpl,
+  q: Parameters)
+  extends BaseTile(myParams, crossing, lookup, q)
+  with SinksExternalInterrupts
+  with SourcesExternalNotifications
+{
+
+  // Private constructor ensures altered LazyModule.p is used implicitly
+  def this(params: MyTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
+    this(params, crossing.crossingType, lookup, p)
+
+  // Require TileLink nodes
+  val intOutwardNode = IntIdentityNode()
+  val masterNode = visibilityNode
+  val slaveNode = TLIdentityNode()
+
+  // Implementation class (See below)
+  override lazy val module = new MyTileModuleImp(this)
+
+  // Required entry of CPU device in the device tree for interrupt purpose
+  val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("my-organization,my-cpu", "riscv")) {
+    override def parent = Some(ResourceAnchors.cpus)
+    override def describe(resources: ResourceBindings): Description = {
+      val Description(name, mapping) = super.describe(resources)
+      Description(name, mapping ++
+                        cpuProperties ++
+                        nextLevelCacheProperty ++
+                        tileProperties)
+    }
+  }
+
+  ResourceBinding {
+    Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
+  }
+
+  // TODO: Create TileLink nodes and connections here.
+  // DOC include end: Tile class
+  
+  // DOC include start: AXI4 node
+  // # of bits used in TileLink ID for master node. 4 bits can support 16 master nodes, but you can have a longer ID if you need more. 
+  val idBits = 4
+  val memAXI4Node = AXI4MasterNode(
+    Seq(AXI4MasterPortParameters(
+      masters = Seq(AXI4MasterParameters(
+        name = "myPortName",
+        id = IdRange(0, 1 << idBits))))))
+  val memoryTap = TLIdentityNode() // Every bus connection should have their own tap node
+  // DOC include end: AXI4 node
+
+  // DOC include start: AXI4 convert
+  (tlMasterXbar.node  // tlMasterXbar is the bus crossbar to be used when this core / tile is acting as a master; otherwise, use tlSlaveXBar
+    := memoryTap
+    := TLBuffer()
+    := TLFIFOFixer(TLFIFOFixer.all) // fix FIFO ordering
+    := TLWidthWidget(masterPortBeatBytes) // reduce size of TL
+    := AXI4ToTL() // convert to TL
+    := AXI4UserYanker(Some(2)) // remove user field on AXI interface. need but in reality user intf. not needed
+    := AXI4Fragmenter() // deal with multi-beat xacts
+    := memAXI4Node) // The custom node, see below
+  // DOC include end: AXI4 convert
+
+}
+
+// DOC include start: Implementation class
+class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
+  // annotate the parameters
+  Annotated.params(this, outer.myParams)
+
+  // TODO: Create the top module of the core and connect it with the ports in "outer"
+
+  // If your core is in Verilog (assume your blackbox is called "MyCoreBlackbox"), instantiate it here like 
+  //   val core = Module(new MyCoreBlackbox(params...)) 
+  // (as described in the blackbox tutorial) and connect appropriate signals. See the blackbox tutorial
+  // (link on the top of the page) for more info.
+  // You can look at https://github.com/ucb-bar/ariane-wrapper/blob/master/src/main/scala/ArianeTile.scala
+  // for a Verilog example.
+
+  // If your core is in Chisel, you can simply instantiate the top module here like other Chisel module
+  // and connect appropriate signal. You can even implement this class as your top module.
+  // See https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/common/tile.scala and
+  // https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/tile/RocketTile.scala for 
+  // Chisel example.
+
+  // DOC include end: Implementation class
+
+  // DOC include start: connect interrupt
+  // For example, our core support debug interrupt and machine-level interrupt, and suppose the following two signals
+  // are the interrupt inputs to the core. (DO NOT COPY this code - if your core treat each type of interrupt differently,
+  // you need to connect them to different interrupt ports of your core)
+  val debug_i = Wire(Bool())
+  val mtip_i = Wire(Bool())
+  // We create a bundle here and decode the interrupt.
+  val int_bundle = new TileInterrupts()
+  outer.decodeCoreInterrupts(int_bundle)
+  debug_i := int_bundle.debug
+  mtip_i := int_bundle.meip & int_bundle.msip & int_bundle.mtip
+  // DOC include end: connect interrupt
+
+  // DOC include start: raise interrupt
+  // This is a demo. You should call these function according to your core
+  // Suppose that the following signal is from the decoder indicating a WFI instruction is received.
+  val wfi_o = Wire(Bool())
+  outer.reportWFI(Some(wfi_o))
+  // Suppose that the following signal indicate an unreconverable hardware error.
+  val halt_o = Wire(Bool())
+  outer.reportHalt(Some(halt_o))
+  // Suppose that our core never stall for a long time / stop retiring. Use None to indicate that this interrupt never fires.
+  outer.reportCease(None)
+  // DOC include end: raise interrupt
+
+  // DOC include start: AXI4 connect
+  outer.memAXI4Node.out foreach { case (out, edgeOut) =>
+    // Connect your module IO port to "out"
+    // The type of "out" here is AXI4Bundle, which is defined in generators/rocket-chip/src/main/scala/amba/axi4/Bundles.scala
+    // Please refer to this file for the definition of the ports.
+    // If you are using APB, check APBBundle in generators/rocket-chip/src/main/scala/amba/apb/Bundles.scala
+    // If you are using AHB, check AHBSlaveBundle or AHBMasterBundle in generators/rocket-chip/src/main/scala/amba/ahb/Bundles.scala
+    // (choose one depends on the type of AHB node you create)
+    // If you are using AXIS, check AXISBundle and AXISBundleBits in generators/rocket-chip/src/main/scala/amba/axis/Bundles.scala
+  }
+  // DOC include end: AXI4 connect
+
+}
+
+// DOC include start: Config fragment
+class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => {
+    // Calculate the next available hart ID (since hart ID cannot be duplicated)
+    val prev = up(TilesLocated(InSubsystem), site)
+    val idOffset = overrideIdOffset.getOrElse(prev.size)
+    // Create TileAttachParams for every core to be instantiated
+    (0 until n).map { i =>
+      MyTileAttachParams(
+        tileParams = MyTileParams(hartId = i + idOffset),
+        crossingParams = RocketCrossingParams()
+      )
+    } ++ prev
+  }
+  // Configurate # of bytes in one memory / IO transaction. For RV64, one load/store instruction can transfer 8 bytes at most.
+  case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
+  // The # of instruction bits. Use maximum # of bits if your core supports both 32 and 64 bits.
+  case XLen => 64
+})
+// DOC include end: Config fragment

generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala

@@ -15,10 +15,12 @@ import firrtl.options.Viewer.view
 import freechips.rocketchip.stage.RocketChipOptions
 import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
 import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
+import freechips.rocketchip.subsystem.{TilesLocated, InSubsystem}
 import freechips.rocketchip.util.HasRocketChipStageUtils
 import freechips.rocketchip.tile.XLen
 
 import chipyard.TestSuiteHelper
+import chipyard.TestSuitesKey
 
 class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
   // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
@@ -33,25 +35,11 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
     val suiteHelper = new TestSuiteHelper
     // Use Xlen as a proxy for detecting if we are a processor-like target
     // The underlying test suites expect this field to be defined
-    if (p.lift(XLen).nonEmpty) {
+    val tileParams = p(TilesLocated(InSubsystem)) map (tp => tp.tileParams)
-      suiteHelper.addRocketTestSuites
+    if (p.lift(XLen).nonEmpty)
-      suiteHelper.addBoomTestSuites
+      // If a custom test suite is set up, use the custom test suite
-      suiteHelper.addArianeTestSuites
+      annotations += CustomMakefragSnippet(p(TestSuitesKey).apply(tileParams, suiteHelper, p))
-    }
 
-    // if hwacha parameter exists then generate its tests
-    // TODO: find a more elegant way to do this. either through
-    // trying to disambiguate BuildRoCC, having a AccelParamsKey,
-    // or having the Accelerator/Tile add its own tests
-    import hwacha.HwachaTestSuites._
-    if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
-      suiteHelper.addSuites(rv64uv.map(_("p")))
-      suiteHelper.addSuites(rv64uv.map(_("vp")))
-      suiteHelper.addSuite(rv64sv("p"))
-      suiteHelper.addSuite(hwachaBmarks)
-      annotations += CustomMakefragSnippet(
-        "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha")
-    }
     RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations
   }
 

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -26,7 +26,7 @@ import ariane.ArianeTile
 
 import boom.common.{BoomTile}
 
-import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
+import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters}
 import testchipip.{CanHaveTraceIOModuleImp}
 
 object MainMemoryConsts {
@@ -56,17 +56,20 @@ class WithBlockDeviceBridge extends OverrideIOBinder({
 
 
 class WithFASEDBridge extends OverrideIOBinder({
-  (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
+  (system: CanHaveMasterAXI4MemPort) => {
-    implicit val p = system.p
+    implicit val p: Parameters = GetSystemParameters(system)
     (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) =>
       val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
                                      axi4.ar.bits.addr.getWidth,
                                      axi4.ar.bits.id.getWidth)
-      FASEDBridge(system.module.clock, axi4, system.module.reset.toBool,
+      system match {
-        CompleteConfig(p(firesim.configs.MemModelKey),
+        case s: BaseSubsystem => FASEDBridge(s.module.clock, axi4, s.module.reset.toBool,
-                       nastiKey,
+          CompleteConfig(p(firesim.configs.MemModelKey),
-                       Some(AXI4EdgeSummary(edge)),
+                         nastiKey,
-                       Some(MainMemoryConsts.globalName)))
+                         Some(AXI4EdgeSummary(edge)),
+                         Some(MainMemoryConsts.globalName)))
+        case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design")
+      }
     })
     Nil
   }

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -69,7 +69,8 @@ class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small")
 class WithFireSimConfigTweaks extends Config(
   // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
   new WithBootROM ++
-  // Optional*: Removing this will require target-software changes to properly capture UART output
+  // Optional*: Removing this will require adjusting the UART baud rate and
+  // potential target-software changes to properly capture UART output
   new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
   // Required: Existing FAME-1 transform cannot handle black-box clock gates
   new WithoutClockGating ++
@@ -85,8 +86,8 @@ class WithFireSimConfigTweaks extends Config(
   new testchipip.WithTSI ++
   // Optional: Removing this will require using an initramfs under linux
   new testchipip.WithBlockDevice ++
-  // Required*:
+  // Required*: Scale default baud rate with periphery bus frequency
-  new chipyard.config.WithUART
+  new chipyard.config.WithUART(BigInt(3686400L))
 )
 
 /*******************************************************************************
@@ -117,6 +118,21 @@ class FireSimQuadRocketConfig extends Config(
   new WithFireSimConfigTweaks ++
   new chipyard.QuadRocketConfig)
 
+// A stripped down configuration that should fit on all supported hosts.
+// Flat to avoid having to reorganize the config class hierarchy to remove certain features 
+class FireSimSmallSystemConfig extends Config(
+  new WithDefaultFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithBootROM ++
+  new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
+  new WithoutClockGating ++
+  new WithoutTLMonitors ++
+  new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
+  new testchipip.WithTSI ++
+  new testchipip.WithBlockDevice ++
+  new chipyard.config.WithUART ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++
+  new chipyard.RocketConfig)
 
 //*****************************************************************
 // Boom config, base off chipyard's LargeBoomConfig

generators/tracegen/tracegen.mk

@@ -9,7 +9,7 @@ $(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh
 	cd $(AXE_DIR) && ./make.sh
 
 $(output_dir)/tracegen.out: $(sim)
-	mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none </dev/null 2> $@
+	mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none </dev/null 2> $@
 
 $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE)
 	$(base_dir)/scripts/check-tracegen.sh $< > $@

generators/utilities/src/main/resources/csrc/emulator.cc

@@ -116,7 +116,6 @@ int main(int argc, char** argv)
   FILE * vcdfile = NULL;
   uint64_t start = 0;
 #endif
-  char ** htif_argv = NULL;
   int verilog_plusargs_legal = 1;
 
   opterr = 1;
@@ -252,10 +251,6 @@ done_processing:
     usage(argv[0]);
     return 1;
   }
-  int htif_argc = 1 + argc - optind;
-  htif_argv = (char **) malloc((htif_argc) * sizeof (char *));
-  htif_argv[0] = argv[0];
-  for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++];
 
   if (verbose)
     fprintf(stderr, "using random seed %u\n", random_seed);
@@ -278,8 +273,8 @@ done_processing:
 #endif
 
   jtag = new remote_bitbang_t(rbb_port);
-  dtm = new dtm_t(htif_argc, htif_argv);
+  dtm = new dtm_t(argc, argv);
-  tsi = new tsi_t(htif_argc, htif_argv);
+  tsi = new tsi_t(argc, argv);
 
   signal(SIGTERM, handle_sigterm);
 
@@ -364,6 +359,5 @@ done_processing:
   if (tsi) delete tsi;
   if (jtag) delete jtag;
   if (tile) delete tile;
-  if (htif_argv) free(htif_argv);
   return ret;
 }

scripts/smartelf2hex.sh

@@ -0,0 +1,14 @@
+#!/usr/bin/env bash
+
+# This script find the appropriate arguments to pass to elf2hex by inspecting the given RISC-V elf binary
+# First and only argument is the binary to be converted.
+# The output of this script should be redirected to a file (as with normal elf2hex).
+
+binary=$1
+segments=`readelf --segments --wide $binary`
+entry_hex=`echo -e "$segments" | grep "Entry point" | cut -f3 -d' ' | sed 's/0x//' | tr [:lower:] [:upper:]`
+entry_dec=`bc <<< "ibase=16;$entry_hex"`
+length_hex=`echo "$segments" | grep LOAD | tail -n 1 | tr -s [:space:] | cut -f4,6 -d' '`
+length_dec=`echo $length_hex | tr -d x | tr [:lower:] [:upper:] | tr ' ' + | sed 's/^/ibase=16;/' | sed "s/$/-$entry_hex/" | bc`
+power_2_length=`echo "x=l($length_dec)/l(2); scale=0; 2^((x+1)/1)" | bc -l`
+elf2hex 64 $power_2_length $binary $entry_dec

scripts/tutorial-patches/RocketConfigs.scala.patch

@@ -1,13 +1,13 @@
 diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
-index f29c580..0bd36ca 100644
+index 8e6e486..fc3a811 100644
 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
 +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
-@@ -333,7 +333,7 @@ class Sha3RocketConfig extends Config(
+@@ -105,7 +105,7 @@ class GB1MemoryRocketConfig extends Config(
-   new chipyard.config.WithBootROM ++
+ 
-   new chipyard.config.WithUART ++
+ // DOC include start: Sha3Rocket
-   new chipyard.config.WithL2TLBs(1024) ++
+ class Sha3RocketConfig extends Config(
 -  new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
 +//  new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
-   new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-   new freechips.rocketchip.subsystem.WithNoSlavePort ++
+   new chipyard.config.AbstractConfig)
-   new freechips.rocketchip.subsystem.WithInclusiveCache ++
+ // DOC include end: Sha3Rocket

sims/vcs/Makefile

@@ -47,13 +47,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(E
 # vcs simulator rules
 #########################################################################################
 $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
-	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@
-	-debug_pp
 
 $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
-	+define+DEBUG \
+	+define+DEBUG
-	-debug_pp
 
 #########################################################################################
 # create a vcs vpd rule

sims/verilator/Makefile

@@ -30,6 +30,13 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
 
 WAVEFORM_FLAG=-v$(sim_out_name).vcd
 
+# If verilator seed unspecified, verilator uses srand as random seed
+ifdef RANDOM_SEED
+SEED_FLAG=+verilator+seed+I$(RANDOM_SEED)
+else
+SEED_FLAG=
+endif
+
 .PHONY: default debug
 default: $(sim)
 debug: $(sim_debug)
@@ -145,7 +152,7 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib)
 $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	rm -f $@.vcd && mkfifo $@.vcd
 	vcd2vpd $@.vcd $@ > /dev/null &
-	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
+	(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
 
 #########################################################################################
 # general cleanup rule

variables.mk

@@ -152,6 +152,8 @@ define run_scala_main
 endef
 endif
 
+FIRRTL_LOGLEVEL ?= error
+
 #########################################################################################
 # output directory for tests
 #########################################################################################
@@ -163,9 +165,15 @@ output_dir=$(sim_dir)/output/$(long_name)
 PERMISSIVE_ON=+permissive
 PERMISSIVE_OFF=+permissive-off
 BINARY ?=
+LOADMEM ?=
+LOADMEM_ADDR ?= 81000000
 override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles)
+ifneq ($(LOADMEM),)
+override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR)
+endif
 VERBOSE_FLAGS ?= +verbose
 sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY))))
+binary_hex= $(sim_out_name).loadmem_hex
 
 #########################################################################################
 # build output directory for compilation

vcs.mk

@@ -1,5 +1,13 @@
 WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd
 
+# If ntb_random_seed unspecified, vcs uses 1 as constant seed.
+# Set ntb_random_seed_automatic to actually get a random seed
+ifdef RANDOM_SEED
+SEED_FLAG=+ntb_random_seed=$(RANDOM_SEED)
+else
+SEED_FLAG=+ntb_random_seed_automatic
+endif
+
 CLOCK_PERIOD ?= 1.0
 RESET_DELAY ?= 777.7
 

vlsi/.gitignore

@@ -4,3 +4,4 @@ hammer*.log
 build
 src/test/output-*.json
 generated-src
+output.json

vlsi/Makefile

@@ -19,25 +19,27 @@ include $(base_dir)/variables.mk
 #########################################################################################
 sim_name           ?= vcs # needed for GenerateSimFiles, but is unused
 tech_name          ?= asap7
-tech_dir           ?= $(if $(filter $(tech_name), asap7), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
+tech_dir           ?= $(if $(filter $(tech_name),asap7 nangate45),\
+                        $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), \
+                        $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name))
 SMEMS_COMP         ?= $(tech_dir)/sram-compiler.json
 SMEMS_CACHE        ?= $(tech_dir)/sram-cache.json
 SMEMS_HAMMER       ?= $(build_dir)/$(long_name).mems.hammer.json
-ifeq ($(tech_name),asap7)
+MACROCOMPILER_MODE ?= $(if $(filter $(tech_name),asap7),\
-	MACROCOMPILER_MODE ?= --mode synflops
+                        --mode synflops,\
-else
+                        -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict)
-	MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER)
-endif
 ENV_YML            ?= $(vlsi_dir)/env.yml
-INPUT_CONFS        ?= example.yml
+INPUT_CONFS        ?= $(if $(filter $(tech_name),nangate45),\
-HAMMER_EXEC        ?= ./example-vlsi
+                        example-nangate45.yml,\
+                        example-asap7.yml)
+HAMMER_EXEC        ?= example-vlsi
 VLSI_TOP           ?= $(TOP)
 VLSI_HARNESS_DUT_NAME ?= dut
 VLSI_OBJ_DIR       ?= $(vlsi_dir)/build
-ifneq ($(CUSTOM_VLOG), )
+ifneq ($(CUSTOM_VLOG),)
-	OBJ_DIR        ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
+	OBJ_DIR          ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
 else
-	OBJ_DIR        ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
+	OBJ_DIR          ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
 endif
 
 #########################################################################################

vlsi/example-nangate45.yml

@@ -0,0 +1,73 @@
+#----------------------
+# Technology Setup
+#----------------------
+
+vlsi.core.technology: nangate45
+
+# the nangate45.tech.json can't reference the $OPENROAD environment variable,
+# so we need to set the install dir here. 
+# TODO: figure out how to remove this, or override it within OpenROADTool
+technology.nangate45.install_dir: "/k/work/OpenROAD-flow/tools/OpenROAD"
+
+vlsi.core.max_threads: 12
+
+#----------------------
+# General Hammer Inputs
+#----------------------
+
+# Hammer will auto-generate a CPF for simple power designs; 
+# see hammer/src/hammer-vlsi/defaults.yml for more info
+vlsi.inputs.power_spec_mode: "auto"
+vlsi.inputs.power_spec_type: "cpf"
+
+# Specify clock signals
+vlsi.inputs.clocks: [
+  {name: "clock", period: "5ns", uncertainty: "0.5ns"}
+]
+
+# Generate Make include to aid in flow 
+vlsi.core.build_system: make
+
+#----------------------
+# Placement Constraints
+#----------------------
+
+# For nangate45, size should be multiple of (0.19,1.4) placement grid
+vlsi.inputs.placement_constraints:
+  - path: "ChipTop"
+    type: toplevel
+    x: 0
+    y: 0
+    width: 3334.72
+    height: 3798.2
+    margins: 
+      left: 0
+      right: 0
+      top: 0
+      bottom: 0
+
+# SRAM Compiler compiler options
+vlsi.core.sram_generator_tool: "sram_compiler"
+## You should specify a location for the SRAM generator in the tech plugin
+vlsi.core.sram_generator_tool_path: [
+  "hammer/src/hammer-vlsi/technology/nangate45"]
+vlsi.core.sram_generator_tool_path_meta: "append"
+
+#----------------------
+# Tool options. Replace with your tool plugin of choice.
+#----------------------
+
+# OpenROAD-yosys options
+vlsi.core.synthesis_tool: "yosys"
+vlsi.core.synthesis_tool_path: ["hammer/src/hammer-vlsi/synthesis/yosys"]
+vlsi.core.synthesis_tool_path_meta: "append"
+
+# OpenROAD-par options
+vlsi.core.par_tool: "openroad"
+vlsi.core.par_tool_path: ["hammer/src/hammer-vlsi/par"]
+vlsi.core.par_tool_path_meta: "append"
+
+# OpenROAD-drc options (no lvs)
+vlsi.core.drc_tool: "openroad"
+vlsi.core.drc_tool_path: ["hammer/src/hammer-vlsi/drc"]
+vlsi.core.drc_tool_path_meta: "append"

vlsi/example-vlsi

@@ -1,4 +1,8 @@
 #!/usr/bin/env python3
+#
+# NOTE: this ExampleDriver works for asap7 and nangate45. the custom hooks are
+# only used for asap7 though.
+
 import os
 
 import hammer_vlsi
@@ -7,21 +11,24 @@ from hammer_vlsi import CLIDriver, HammerToolHookAction
 from typing import Dict, Callable, Optional, List
 
 def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool:
-    x.append('''
+    if x.get_setting("vlsi.core.technology") == "asap7":
+        x.append('''
 # TODO
 # Place custom TCL here
 ''')
     return True
 
 def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool:
-    x.append('''
+    if x.get_setting("vlsi.core.technology") == "asap7":
+        x.append('''
 # TODO
 # Place custom TCL here
 ''')
     return True
 
 def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
-    x.append('''
+    if x.get_setting("vlsi.core.technology") == "asap7":
+        x.append('''
 # TODO
 # Place custom TCL here
 set_db route_design_bottom_routing_layer 2
@@ -34,7 +41,8 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool:
     Scale the final GDS by a factor of 4
     hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script
     """
-    x.append('''
+    if x.get_setting("vlsi.core.technology") == "asap7":
+        x.append('''
 # Write script out to a temporary file and execute it
 set fp [open "{script_file}" "w"]
 puts -nonewline $fp "{script_text}"