diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala
index 919e5c99..8f0b7143 100644
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -26,7 +26,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
   val harnessClock = clock_32MHz
   val harnessReset = hReset
   val success = false.B
-  val dutReset = hReset
+  val dutReset = reset_core
 
   // must be after HasHarnessSignalReferences assignments
   ldut.harnessFunctions.foreach(_(this))
diff --git a/fpga/src/main/scala/arty/e300/IOBinders.scala b/fpga/src/main/scala/arty/e300/IOBinders.scala
index 8d866619..6cab4b1e 100644
--- a/fpga/src/main/scala/arty/e300/IOBinders.scala
+++ b/fpga/src/main/scala/arty/e300/IOBinders.scala
@@ -56,10 +56,8 @@ class WithE300Connections extends OverrideIOBinder({
     val io_jtag_reset = IO(Input(Bool())).suggestName("jtag_reset")
     val io_ndreset    = IO(Output(Bool())).suggestName("ndreset")
 
-    // This needs to be de-asserted synchronously to the coreClk.
-    val async_corerst = system.aon.rsts.corerst
-    // Add in debug-controlled reset.
-    system.reset := ResetCatchAndSync(system.clock, async_corerst, 20)
+    val io_async_corerst = IO(Input(Bool())).suggestName("core_reset")
+    system.reset := ResetCatchAndSync(system.clock, io_async_corerst, 20)
     Debug.connectDebugClockAndReset(system.debug, system.clock)
 
     //-----------------------------------------------------------------------
@@ -186,6 +184,8 @@ class WithE300Connections extends OverrideIOBinder({
     val harnessFn = (baseTh: HasHarnessSignalReferences) => {
       baseTh match { case th: ArtyShell =>
 
+        io_async_corerst := th.reset_core
+
         //-----------------------------------------------------------------------
         // Clock divider
         //-----------------------------------------------------------------------