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Fix pin mappings for TSI DDR

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This commit is contained in:
Abraham Gonzalez
2020-11-06 20:51:11 -08:00
parent 7baa1341ee
commit 9144e3c706
1 changed files with 1 additions and 1 deletions
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2
fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
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@@ -261,7 +261,7 @@ class TSIHostVCU118PlacedOverlay(val shell: BringupVCU118FPGATestHarness, name:
"BF30", "AY34", "AU29", "AP31", "BE35", "BE39", "BA35", "AW37", // dqs_t[0->7]
"BE32", "BB31", "AV33", "AR32", "BC34", "BE40", "AY37", "AV35") // dm_dbi_n[0->7]
(IOPin.of(io) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) }
(IOPin.of(io.ddr) zip allddrpins) foreach { case (io, pin) => shell.xdc.addPackagePin(io, pin) }
} }
shell.sdc.addGroup(pins = Seq(mig.island.module.blackbox.io.c0_ddr4_ui_clk))