diff --git a/CHANGELOG.md b/CHANGELOG.md index 8e7ed003..233ddbce 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,89 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.10.0] - 2023-6-16 + +Adds superscalar in-order core, prefetchers, architectural checkpointing, examples for custom-chiptop/tapeout-chip/flat-chiptop. FireSim bumped with new local FPGA support: Xilinx VCU118 (w/XDMA), Xilinx Alveo U250/U280 (w/XDMA, in addition to previous Vitis support), RHSResearch NiteFury II (w/XDMA). FireSim now also supports Xcelium for metasims. + +### Added +* QoL improvement to IOBinders + custom ChipTop example by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1399 +* New Scala-based Config Finder by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1424 +* ADD: improve Makefile in tests/, add explicit arch flags by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1439 +* Add mt-helloworld example by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1428 +* Add tutorial software by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1447 +* Support not instantiating the TileClockGater/ResetSetter PRCI control by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1459 +* ELF-based-loadmem | architectural restartable checkpoints by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1438 +* Add embench build support by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1479 +* Support multi-run of binaries by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1480 +* Integrate barf (prefetchers) by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1505 +* Add higher level explanations of RoCC + more resources by @nikhiljha in https://github.com/ucb-bar/chipyard/pull/1486 +* Support banked/partitioned scratchpads by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1431 +* Add dual-issue in-order "shuttle" core by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1495 +* Improve peripheral fragments to include more peripheral devices and support instantiating multiple instances of same device by @T-K-233 in https://github.com/ucb-bar/chipyard/pull/1511 + +### Changed +* Bump to latest rocket-chip/chisel3.5.6 by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1411 +* Resolve merge conflicts in chisel3.5.6 bump by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1430 +* PLL integration example + FlatChipTop/TestHarness by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1427 +* bump testchipip by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1434 +* Fix ChipLikeQuadRocketConfig crossing by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1436 +* Bump TestChipIp to improve default serial_tl behavior by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1435 +* Bump testchipip to standardize TL serdesser bundle params by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1446 +* Bump to Hammer 1.1.1 by @harrisonliew in https://github.com/ucb-bar/chipyard/pull/1451 +* Always initialize fpga-shells with init-submodules.sh by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1456 +* Support uni-directional TLSerdesser by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1476 +* Move xcelium.mk out of top-level by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1482 +* Set default config back to 1-channel by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1483 +* Unify supernode/harness-clocking across chipyard/firesim/fpga by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1474 +* Use fat jar's to remove SBT invocations by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1375 +* Bump to latest rocket-chip by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1475 +* Improvements to chipyard clocking by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1489 +* Downgrade cryptography | Pin linux sysroot by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1494 +* bump mempress by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1498 +* bump sha3 by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1499 +* Bump FireMarshal by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1502 +* Split NVDLA config out of ManyMMIOAccels config to reduce CI load by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1503 +* Ignore barstools compilation if not needed by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1504 +* Disable NVDLA simulations in CI by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1507 +* Update NoC example config to match new PRCI organization by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1509 +* Bump gemmini by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1519 + +### Fixed +* Various improvements and fixes by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1420 +* Ensure conda cleanup regex properly filters out non-numeric chars by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1425 +* Clear screen on prompt by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1449 +* misc: many fixes to cospike by @tianrui-wei in https://github.com/ucb-bar/chipyard/pull/1450 +* Uniquify module names that are common to Top & Model by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1442 +* Use pk/encoding.h for hello/mt-hello by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1454 +* Fix no-uart configs by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1457 +* Fix support for no-bootROM systems by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1458 +* Check that HarnessClockInstantiator doesn't receive requests for similarly-named-clocks with different frequencies by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1460 +* uniquify module names by @joey0320 in https://github.com/ucb-bar/chipyard/pull/1452 +* Flip serial_tl_clock to be generated off-chip by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1445 +* Move TestHarness to chipyard.harness, make chipyard/harness directory by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1463 +* Separate out conda-lock generation into new script by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1466 +* Bump DRAMSim2 to avoid verbose log files by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1468 +* Bump Verilator and use `TestDriver.v` as top by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1398 +* Add 1GB / 4GB DRAM firechip configs for FireSim VCU118 by @sagark in https://github.com/ucb-bar/chipyard/pull/1471 +* Rename SerialAdapter+SimSerial to TSIToTileLink/SimTSI/TSIHarness by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1465 +* Make BootAddrReg optional by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1464 +* Fix vcd/fst/fsdb waveform generation by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1473 +* Switch RTL sims to absolute clock-generators by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1472 +* Generate objdump | check BINARY | cospike fixes by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1467 +* Small QOL fixes for Xcelium by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1485 +* (VCU118 DDR HarnessBinder)Fix data field width mismatch between DDR AXI and TileLink MemoryBus by @jerryhethatday in https://github.com/ucb-bar/chipyard/pull/1487 +* Force conda-lock to v1 by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1492 +* Loosen/tighten conda requirements | Fix conda-lock req by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1497 +* Misc Makefile Fixes by @abejgonzalez in https://github.com/ucb-bar/chipyard/pull/1496 +* Bump constellation to fix interconnect FIFO-fixers by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1510 +* [ci skip] Fix broken docs link by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1515 +* Revert changes to peripheral fragments by @jerryz123 in https://github.com/ucb-bar/chipyard/pull/1518 + +### New Contributors +* @tianrui-wei made their first contribution in https://github.com/ucb-bar/chipyard/pull/1450 +* @jerryhethatday made their first contribution in https://github.com/ucb-bar/chipyard/pull/1487 +* @nikhiljha made their first contribution in https://github.com/ucb-bar/chipyard/pull/1486 + ## [1.9.1] - 2023-04-21 Various fixes for Linux boot, More Chip/bringup examples, Chisel 3.5.6 bump diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 703561fe..0e126252 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -26,9 +26,9 @@ Finally, source the following environment at the root of the FireSim directory: cd sims/firesim # (Recommended) The default manager environment (includes env.sh) - source sourceme-f1-manager.sh + source sourceme-manager.sh -.. Note:: Every time you want to use FireSim with a fresh shell, you must source this ``sourceme-f1-manager.sh`` +.. Note:: Every time you want to use FireSim with a fresh shell, you must source ``sourceme-manager.sh`` At this point you're ready to use FireSim with Chipyard. If you're not already familiar with FireSim, please return to the :fsim_doc:`FireSim Docs `, diff --git a/generators/boom b/generators/boom index f732ceb6..1a153d49 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit f732ceb602bcccd4adb6a5f7137c7c0bea08be9d +Subproject commit 1a153d4974977a2d5f8baa9b4de51b3337d230fe diff --git a/generators/constellation b/generators/constellation index e9f1c828..8184e0e7 160000 --- a/generators/constellation +++ b/generators/constellation @@ -1 +1 @@ -Subproject commit e9f1c828ca5adb4fa46a242cd1798391fc9e6f62 +Subproject commit 8184e0e7e32ff11dce344c449158aa7551e164e0 diff --git a/generators/gemmini b/generators/gemmini index 80e7376c..f13847e8 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 80e7376cf554ed302975d72ed091ac86a9e553e8 +Subproject commit f13847e839baee4a3c8d5d51e76a3dc9e9c1933f diff --git a/generators/testchipip b/generators/testchipip index 1438f7c0..68d5c565 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 1438f7c0e3c9907de48cdbb0b4cd8c5855eff77d +Subproject commit 68d5c565413eac9b1e3bb3e7ff4d477d0cd2512e diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh index 02e1fd81..443ffabd 100755 --- a/scripts/build-setup.sh +++ b/scripts/build-setup.sh @@ -178,7 +178,7 @@ if run_step "6"; then pushd $CYDIR/sims/firesim ( echo $CYDIR - source sourceme-f1-manager.sh --skip-ssh-setup + source sourceme-manager.sh --skip-ssh-setup pushd sim make sbt SBT_COMMAND="project {file:$CYDIR}firechip; compile" TARGET_PROJECT=firesim popd diff --git a/sims/firesim b/sims/firesim index b0007729..b0f276fb 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit b0007729905bb3be4125440924ecc97bed9ecf88 +Subproject commit b0f276fba6ec0e32f3059fc850a7d34072bf29d3 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index dcd9eb21..fe641d1c 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit dcd9eb212aefd8040cdf9c50adffbbf975422a1d +Subproject commit fe641d1c346d5605f95d235e8c75d0baac7fa6d8 diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index dbcadab0..6fc819aa 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "1ns", uncertainty: "0.1ns"} + {name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index ebc2d6a6..3f46a443 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "2ns", uncertainty: "0.1ns"} + {name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"} ] # Specify pin properties diff --git a/vlsi/example-designs/sky130-commercial.yml b/vlsi/example-designs/sky130-commercial.yml index b2ecfb26..c4377d22 100644 --- a/vlsi/example-designs/sky130-commercial.yml +++ b/vlsi/example-designs/sky130-commercial.yml @@ -2,7 +2,7 @@ # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "30ns", uncertainty: "2ns"} + {name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"} ] # Placement Constraints @@ -16,4 +16,4 @@ vlsi.inputs.clocks: [ # - path: "ChipTop" # ... # margins: -# right: 0 # or left: 0 \ No newline at end of file +# right: 0 # or left: 0 diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml index 752facfd..a3fed011 100644 --- a/vlsi/example-designs/sky130-openroad-rockettile.yml +++ b/vlsi/example-designs/sky130-openroad-rockettile.yml @@ -1,7 +1,7 @@ # Override configurations in ../example-sky130.yml and example-designs # Specify clock signals -# Rocket/RocketTile names clock signal "clock" instead of "clock_clock" +# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock" vlsi.inputs.clocks: [ {name: "clock", period: "30ns", uncertainty: "3ns"} ] diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index b52266b4..669d2f92 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -3,7 +3,7 @@ # Specify clock signals # Relax the clock period for OpenROAD to meet timing vlsi.inputs.clocks: [ - {name: "clock_clock", period: "50ns", uncertainty: "2ns"} + {name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"} ] # Flow parameters that yield a routable design with reasonable timing diff --git a/vlsi/example-designs/sky130-rocket.yml b/vlsi/example-designs/sky130-rocket.yml index b03d26c5..2e7c7a5b 100644 --- a/vlsi/example-designs/sky130-rocket.yml +++ b/vlsi/example-designs/sky130-rocket.yml @@ -1,7 +1,7 @@ # Override configurations in ../example-sky130.yml and example-designs # Specify clock signals -# Rocket/RocketTile names clock signal "clock" instead of "clock_clock" +# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock" vlsi.inputs.clocks: [ {name: "clock", period: "5ns", uncertainty: "1ns"} ] diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml index 5481c4a8..1cd281f7 100644 --- a/vlsi/example-sky130.yml +++ b/vlsi/example-sky130.yml @@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock_clock", period: "20ns", uncertainty: "1ns"} + {name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"} ] # Generate Make include to aid in flow diff --git a/vlsi/sim.mk b/vlsi/sim.mk index b721c9fb..ea2c76d7 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -21,7 +21,7 @@ $(SIM_CONF): $(sim_common_files) check-binary done echo " options_meta: 'append'" >> $@ echo " defines:" >> $@ - for x in $(subst +define+,,$(PREPROC_DEFINES)); do \ + for x in $(subst +define+,,$(SIM_PREPROC_DEFINES)); do \ echo ' - "'$$x'"' >> $@; \ done echo " defines_meta: 'append'" >> $@ @@ -75,7 +75,7 @@ $(SIM_TIMING_CONF): $(sim_common_files) echo "sim.inputs:" > $@ echo " defines: ['NTC']" >> $@ echo " defines_meta: 'append'" >> $@ - echo " timing_annotated: 'true'" >> $@ + echo " timing_annotated: true" >> $@ # Update hammer top-level sim targets to include our generated sim configs redo-sim-rtl: $(SIM_CONF)