From 9436aea1e8020bf1854ae19804f3b7eb9d10f3d9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 19 Apr 2024 11:30:15 -0700 Subject: [PATCH] Fixes for in-tree barstools --- .github/scripts/check-commit.sh | 2 +- build.sbt | 9 +++------ common.mk | 16 ++++++++-------- docs/Customization/Custom-Chisel.rst | 2 +- generators/chipyard/src/main/scala/ChipTop.scala | 2 +- .../src/main/scala/clocking/ClockBinders.scala | 2 +- .../src/main/scala/example/CustomChipTop.scala | 2 +- .../src/main/scala/example/FlatChipTop.scala | 2 +- .../src/main/scala/harness/HarnessBinders.scala | 2 +- .../src/main/scala/iobinders/IOBinders.scala | 2 +- .../chipyard/src/main/scala/iocell/Analog.scala | 4 ++-- .../chipyard/src/main/scala/iocell/IOCell.scala | 2 +- .../firechip/src/main/scala/BridgeBinders.scala | 2 +- scripts/tutorial-patches/build.sbt.patch | 2 +- .../src/main/scala/macros/CostMetric.scala | 2 +- .../src/main/scala/macros/MacroCompiler.scala | 4 ++-- .../src/main/scala/macros/SynFlopsPass.scala | 4 ++-- tools/tapeout/src/main/scala/macros/Utils.scala | 2 +- .../main/scala/transforms/ExtraTransforms.scala | 2 +- .../transforms/GenerateModelStageMain.scala | 4 ++-- .../main/scala/transforms/retime/Retime.scala | 2 +- .../scala/transforms/stage/TapeoutStage.scala | 4 ++-- .../main/scala/transforms/utils/FileUtils.scala | 2 +- .../transforms/utils/LowerAnnotations.scala | 2 +- .../transforms/utils/ProgrammaticBundle.scala | 2 +- .../scala/transforms/utils/YamlHelpers.scala | 2 +- 26 files changed, 40 insertions(+), 43 deletions(-) diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index 8043c12f..8fa9c24c 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -92,7 +92,7 @@ dir="software" branches=("master" "dev") search -submodules=("DRAMSim2" "axe" "barstools" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde") +submodules=("DRAMSim2" "axe" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde") dir="tools" branches=("master" "dev" "main") search diff --git a/build.sbt b/build.sbt index d929b3ca..03bfeaab 100644 --- a/build.sbt +++ b/build.sbt @@ -158,7 +158,7 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val chipyard = (project in file("generators/chipyard")) - .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell, + .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, rocket_dsp_utils, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, @@ -256,13 +256,10 @@ lazy val rocc_acc_utils = (project in file("generators/rocc-acc-utils")) .settings(libraryDependencies ++= rocketLibDeps.value) .settings(commonSettings) -lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "iocell") - .settings(chiselSettings) - .settings(commonSettings) - -lazy val tapeout = (project in file("./tools/barstools/")) +lazy val tapeout = (project in file("./tools/tapeout/")) .settings(chiselSettings) .settings(commonSettings) + .settings(libraryDependencies ++= Seq("com.typesafe.play" %% "play-json" % "2.9.2")) lazy val fixedpoint = (project in file("./tools/fixedpoint/")) .settings(chiselSettings) diff --git a/common.mk b/common.mk index a2e31b51..ea5811ac 100644 --- a/common.mk +++ b/common.mk @@ -91,9 +91,9 @@ VLOG_EXT = sv v CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src) CHIPYARD_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(SCALA_EXT)) CHIPYARD_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(CHIPYARD_SOURCE_DIRS),$(VLOG_EXT)) -BARSTOOLS_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/barstools) -BARSTOOLS_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(SCALA_EXT)) -BARSTOOLS_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(BARSTOOLS_SOURCE_DIRS),$(VLOG_EXT)) +TAPEOUT_SOURCE_DIRS = $(addprefix $(base_dir)/,tools/tapeout) +TAPEOUT_SCALA_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(SCALA_EXT)) +TAPEOUT_VLOG_SOURCES = $(call lookup_srcs_by_multiple_type,$(TAPEOUT_SOURCE_DIRS),$(VLOG_EXT)) # This assumes no SBT meta-build sources SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools) SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties @@ -127,7 +127,7 @@ $(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEP $(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH)) # order only dependency between sbt runs needed to avoid concurrent sbt runs -$(TAPEOUT_CLASSPATH_TARGETS) &: $(BARSTOOLS_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(BARSTOOLS_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS) +$(TAPEOUT_CLASSPATH_TARGETS) &: $(TAPEOUT_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(TAPEOUT_VLOG_SOURCES) | $(CHIPYARD_CLASSPATH_TARGETS) mkdir -p $(dir $@) $(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH)) @@ -165,7 +165,7 @@ define sfc_extra_low_transforms_anno_contents [ { "class": "firrtl.stage.RunFirrtlTransformAnnotation", - "transform": "barstools.tapeout.transforms.ExtraLowTransforms" + "transform": "tapeout.transforms.ExtraLowTransforms" } ] endef @@ -232,7 +232,7 @@ $(FINAL_ANNO_FILE): $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(SFC_LEVEL) $(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX) $(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(MFC_LOWERING_OPTIONS) rm -rf $(GEN_COLLATERAL_DIR) - $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\ + $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.transforms.GenerateModelStageMain,\ --no-dedup \ --output-file $(SFC_FIRRTL_BASENAME) \ --output-annotation-file $(SFC_ANNO_FILE) \ @@ -297,12 +297,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs TOP_MACROCOMPILER_MODE ?= --mode synflops $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF) - $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE)) + $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE)) touch $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) MODEL_MACROCOMPILER_MODE = --mode synflops $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) - $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE)) + $(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),tapeout.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE)) touch $(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) ######################################################################################## diff --git a/docs/Customization/Custom-Chisel.rst b/docs/Customization/Custom-Chisel.rst index a3b4ef72..19a7bde8 100644 --- a/docs/Customization/Custom-Chisel.rst +++ b/docs/Customization/Custom-Chisel.rst @@ -59,7 +59,7 @@ should look something like this: .. code-block:: scala lazy val chipyard = (project in file("generators/chipyard")) - .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell, + .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, sha3, dsptools, `rocket-dsp-utils`, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, yourproject, // <- added to the middle of the list for simplicity diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index d80d71af..518afa7d 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -10,7 +10,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleI import freechips.rocketchip.util.{DontTouch} import chipyard.iobinders._ -import barstools.iocell.chisel._ +import chipyard.iocell._ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => new DigitalTop()(p)) diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index fdb2ec9e..d075fcbb 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.prci._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ -import barstools.iocell.chisel._ +import chipyard.iocell._ // This uses the FakePLL, which uses a ClockAtFreq Verilog blackbox to generate // the requested clocks. This also adds TileLink ClockDivider and ClockSelector diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala index eb0565ce..5958d1b2 100644 --- a/generators/chipyard/src/main/scala/example/CustomChipTop.scala +++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala @@ -6,7 +6,7 @@ import chipyard.iobinders._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy.{InModuleBody} import freechips.rocketchip.subsystem.{PBUS, HasTileLinkLocations} -import barstools.iocell.chisel._ +import chipyard.iocell._ import chipyard._ import chipyard.harness.{BuildTop} import sifive.blocks.devices.uart._ diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index 6b249286..d8f659f4 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -13,7 +13,7 @@ import chipyard.{BuildSystem, DigitalTop} import chipyard.harness.{BuildTop} import chipyard.clocking._ import chipyard.iobinders._ -import barstools.iocell.chisel._ +import chipyard.iocell._ import testchipip.serdes.{SerialTLKey} class WithFlatChipTop extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index f357f357..9bf97b18 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.devices.debug.{SimJTAG} -import barstools.iocell.chisel._ +import chipyard.iocell._ import testchipip.dram.{SimDRAM} import testchipip.tsi.{SimTSI, SerialRAM, TSI, TSIIO} import testchipip.soc.{TestchipSimDTM} diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index b4f116d2..e00f43a4 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -27,7 +27,7 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import tracegen.{TraceGenSystemModuleImp} -import barstools.iocell.chisel._ +import chipyard.iocell._ import testchipip.serdes.{CanHavePeripheryTLSerial, SerialTLKey} import testchipip.spi.{SPIChipIO} diff --git a/generators/chipyard/src/main/scala/iocell/Analog.scala b/generators/chipyard/src/main/scala/iocell/Analog.scala index 0cdfc493..78e1cfe7 100644 --- a/generators/chipyard/src/main/scala/iocell/Analog.scala +++ b/generators/chipyard/src/main/scala/iocell/Analog.scala @@ -1,6 +1,6 @@ // See LICENSE for license details -package barstools.iocell.chisel +package chipyard.iocell import chisel3._ import chisel3.util.{HasBlackBoxResource} @@ -10,7 +10,7 @@ class AnalogConst(value: Int, width: Int = 1) extends BlackBox(Map("CONST" -> IntParam(value), "WIDTH" -> IntParam(width))) with HasBlackBoxResource { val io = IO(new Bundle { val io = Analog(width.W) }) - addResource("/barstools/iocell/vsrc/Analog.v") + addResource("/vsrc/Analog.v") } object AnalogConst { diff --git a/generators/chipyard/src/main/scala/iocell/IOCell.scala b/generators/chipyard/src/main/scala/iocell/IOCell.scala index d38f8406..5f0129b8 100644 --- a/generators/chipyard/src/main/scala/iocell/IOCell.scala +++ b/generators/chipyard/src/main/scala/iocell/IOCell.scala @@ -1,6 +1,6 @@ // See LICENSE for license details -package barstools.iocell.chisel +package chipyard.iocell import chisel3._ import chisel3.util.{Cat, HasBlackBoxInline} diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 55089358..48ea9bb3 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -26,7 +26,7 @@ import firesim.configs.MemModelKey import tracegen.{TraceGenSystemModuleImp} import cva6.CVA6Tile -import barstools.iocell.chisel._ +import chipyard.iocell._ import chipyard.iobinders._ import chipyard._ import chipyard.harness._ diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index b64d7a43..613790c9 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -5,7 +5,7 @@ index c3be6161..2a6d7160 100644 @@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip")) lazy val chipyard = (project in file("generators/chipyard")) - .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell, + .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, - sha3, // On separate line to allow for cleaner tutorial-setup patches + //sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, rocket_dsp_utils, diff --git a/tools/tapeout/src/main/scala/macros/CostMetric.scala b/tools/tapeout/src/main/scala/macros/CostMetric.scala index 647889d3..1be33967 100644 --- a/tools/tapeout/src/main/scala/macros/CostMetric.scala +++ b/tools/tapeout/src/main/scala/macros/CostMetric.scala @@ -1,6 +1,6 @@ // See LICENSE for license details. -package barstools.macros +package tapeout.macros /** Trait which can calculate the cost of compiling a memory against a certain * library memory macro using a cost function. diff --git a/tools/tapeout/src/main/scala/macros/MacroCompiler.scala b/tools/tapeout/src/main/scala/macros/MacroCompiler.scala index 459992f2..fbf857fe 100644 --- a/tools/tapeout/src/main/scala/macros/MacroCompiler.scala +++ b/tools/tapeout/src/main/scala/macros/MacroCompiler.scala @@ -5,9 +5,9 @@ * lib - technology SRAM(s) to use to compile mem */ -package barstools.macros +package tapeout.macros -import barstools.macros.Utils._ +import tapeout.macros.Utils._ import firrtl.Utils.{one, zero, BoolType} import firrtl.annotations._ import firrtl.ir._ diff --git a/tools/tapeout/src/main/scala/macros/SynFlopsPass.scala b/tools/tapeout/src/main/scala/macros/SynFlopsPass.scala index 5dda0476..0c1dd804 100644 --- a/tools/tapeout/src/main/scala/macros/SynFlopsPass.scala +++ b/tools/tapeout/src/main/scala/macros/SynFlopsPass.scala @@ -1,8 +1,8 @@ // See LICENSE for license details. -package barstools.macros +package tapeout.macros -import barstools.macros.Utils._ +import tapeout.macros.Utils._ import firrtl.Utils.{one, zero} import firrtl._ import firrtl.ir._ diff --git a/tools/tapeout/src/main/scala/macros/Utils.scala b/tools/tapeout/src/main/scala/macros/Utils.scala index 2bcd116f..8715ec10 100644 --- a/tools/tapeout/src/main/scala/macros/Utils.scala +++ b/tools/tapeout/src/main/scala/macros/Utils.scala @@ -1,6 +1,6 @@ // See LICENSE for license details. -package barstools.macros +package tapeout.macros import firrtl.Utils.BoolType import firrtl.ir._ diff --git a/tools/tapeout/src/main/scala/transforms/ExtraTransforms.scala b/tools/tapeout/src/main/scala/transforms/ExtraTransforms.scala index f7ef25c6..4b427653 100644 --- a/tools/tapeout/src/main/scala/transforms/ExtraTransforms.scala +++ b/tools/tapeout/src/main/scala/transforms/ExtraTransforms.scala @@ -1,6 +1,6 @@ // See LICENSE for license details. -package barstools.tapeout.transforms +package tapeout.transforms import firrtl.Mappers._ import firrtl._ diff --git a/tools/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala b/tools/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala index 08cd8d04..5a1a3fdb 100644 --- a/tools/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala +++ b/tools/tapeout/src/main/scala/transforms/GenerateModelStageMain.scala @@ -1,6 +1,6 @@ -package barstools.tapeout.transforms +package tapeout.transforms -import barstools.tapeout.transforms.stage._ +import tapeout.transforms.stage._ import firrtl._ import firrtl.annotations._ import firrtl.ir._ diff --git a/tools/tapeout/src/main/scala/transforms/retime/Retime.scala b/tools/tapeout/src/main/scala/transforms/retime/Retime.scala index 1a9d6668..321f3d42 100644 --- a/tools/tapeout/src/main/scala/transforms/retime/Retime.scala +++ b/tools/tapeout/src/main/scala/transforms/retime/Retime.scala @@ -1,6 +1,6 @@ // See LICENSE for license details. -package barstools.tapeout.transforms.retime +package tapeout.transforms.retime import chisel3.experimental.RunFirrtlTransform import firrtl.annotations._ diff --git a/tools/tapeout/src/main/scala/transforms/stage/TapeoutStage.scala b/tools/tapeout/src/main/scala/transforms/stage/TapeoutStage.scala index cdae1bfd..5fdadf23 100644 --- a/tools/tapeout/src/main/scala/transforms/stage/TapeoutStage.scala +++ b/tools/tapeout/src/main/scala/transforms/stage/TapeoutStage.scala @@ -1,8 +1,8 @@ // See LICENSE for license details. -package barstools.tapeout.transforms.stage +package tapeout.transforms.stage -import barstools.tapeout.transforms.GenerateModelStageMain +import tapeout.transforms.GenerateModelStageMain import chisel3.stage.ChiselCli import firrtl.stage.{RunFirrtlTransformAnnotation} import firrtl.AnnotationSeq diff --git a/tools/tapeout/src/main/scala/transforms/utils/FileUtils.scala b/tools/tapeout/src/main/scala/transforms/utils/FileUtils.scala index 78d33e10..5c18aa18 100644 --- a/tools/tapeout/src/main/scala/transforms/utils/FileUtils.scala +++ b/tools/tapeout/src/main/scala/transforms/utils/FileUtils.scala @@ -1,6 +1,6 @@ // See LICENSE for license details. -package barstools.tapeout.transforms.utils +package tapeout.transforms.utils import chisel3.experimental.{annotate, ChiselAnnotation} import firrtl._ diff --git a/tools/tapeout/src/main/scala/transforms/utils/LowerAnnotations.scala b/tools/tapeout/src/main/scala/transforms/utils/LowerAnnotations.scala index 45502d6d..ef417e2c 100644 --- a/tools/tapeout/src/main/scala/transforms/utils/LowerAnnotations.scala +++ b/tools/tapeout/src/main/scala/transforms/utils/LowerAnnotations.scala @@ -1,4 +1,4 @@ -package barstools.tapeout.transforms.utils +package tapeout.transforms.utils object LowerName { def apply(s: String): String = s.replace(".", "_").replace("[", "_").replace("]", "") diff --git a/tools/tapeout/src/main/scala/transforms/utils/ProgrammaticBundle.scala b/tools/tapeout/src/main/scala/transforms/utils/ProgrammaticBundle.scala index ef98b294..6c277fea 100644 --- a/tools/tapeout/src/main/scala/transforms/utils/ProgrammaticBundle.scala +++ b/tools/tapeout/src/main/scala/transforms/utils/ProgrammaticBundle.scala @@ -1,4 +1,4 @@ -package barstools.tapeout.transforms.utils +package tapeout.transforms.utils import chisel3._ diff --git a/tools/tapeout/src/main/scala/transforms/utils/YamlHelpers.scala b/tools/tapeout/src/main/scala/transforms/utils/YamlHelpers.scala index 9b58e083..0dae7ffa 100644 --- a/tools/tapeout/src/main/scala/transforms/utils/YamlHelpers.scala +++ b/tools/tapeout/src/main/scala/transforms/utils/YamlHelpers.scala @@ -1,4 +1,4 @@ -package barstools.tapeout.transforms.utils +package tapeout.transforms.utils import firrtl.FileUtils import net.jcazevedo.moultingyaml._