diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 0d8f38dd..ffcb6811 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -22,6 +22,7 @@ import icenet._ import firesim.bridges._ import firesim.util.{WithNumNodes, FireSimClockKey, FireSimClockParameters} import firesim.configs._ +import midas.widgets.RationalClock class WithBootROM extends Config((site, here, up) => { case BootROMParams => { @@ -348,7 +349,7 @@ class FireSimTraceGenL2Config extends Config( class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => { - case FireSimClockKey => FireSimClockParameters(Seq(multiplier -> divisor)) + case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) case RocketCrossingKey => up(RocketCrossingKey, site) map { r => r.copy(crossingType = RationalCrossing()) } diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 55761233..653a450f 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -16,6 +16,7 @@ import firesim.bridges.{TracerVBridge} import firesim.util.{HasAdditionalClocks, FireSimClockKey} import midas.targetutils.MemModelAnnotation +import midas.widgets.RationalClock import boom.common.BoomTile @@ -80,7 +81,7 @@ trait CanHaveMultiCycleRegfileImp { trait HasFireSimClockingImp extends HasAdditionalClocks { val outer: HasTiles val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match { - case Some((numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) + case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) case None => (clocks(0), reset) } diff --git a/tools/firrtl b/tools/firrtl index f738fbe8..7eb1c7c0 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit f738fbe8667ed6b76ec00a15960b9c3a42b8654a +Subproject commit 7eb1c7c074713335f252bc8e7b48b9f3e057056c