From 96bf702c3b12cd1c6ed73090904a3609fe85ee95 Mon Sep 17 00:00:00 2001
From: David Biancolin <david.biancolin@gmail.com>
Date: Thu, 24 Sep 2020 23:23:11 -0700
Subject: [PATCH] [clocks] Factor out the PLL calculations into their own class

---
 .../src/main/scala/ConfigFragments.scala      |  2 +-
 .../main/scala/clocking/IdealizedPLL.scala    | 28 ++++++++++++++-----
 2 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala
index 19fe0630..38dea871 100644
--- a/generators/chipyard/src/main/scala/ConfigFragments.scala
+++ b/generators/chipyard/src/main/scala/ConfigFragments.scala
@@ -26,7 +26,7 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
 
-import chipyard.{BuildTop, BuildSystem, ClockingSchemeGenerators, ClockingSchemeKey, TestSuitesKey, TestSuiteHelper, ClockNameContainsAssignment}
+import chipyard._
 
 // Imports for multiclock sketch
 import boom.common.{BoomTile, BoomTileParams}
diff --git a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala
index 6cf03e27..44e58053 100644
--- a/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala
+++ b/generators/chipyard/src/main/scala/clocking/IdealizedPLL.scala
@@ -7,6 +7,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 
 import scala.collection.mutable
+import scala.collection.immutable.ListMap
 
 /**
   * TODO: figure out how much division is acceptable in our simulators and redefine this.
@@ -24,6 +25,23 @@ object FrequencyUtils {
   }
 }
 
+class SimplePllConfiguration(val sinks: Seq[ClockSinkParameters]) {
+  val referenceFreqMHz = FrequencyUtils.computeReferenceFrequencyMHz(sinks.flatMap(_.take)).freqMHz
+  val sinkDividerMap = ListMap((sinks.map({s => (s, Math.round(referenceFreqMHz / s.take.get.freqMHz).toInt) })):_*)
+
+  def prettyPrint(pllName: String) {
+    val preamble = s"""
+    |${pllName} Frequency Summary
+    |  Input Reference Frequency: ${referenceFreqMHz} MHz\n""".stripMargin
+    val outputSummaries = sinkDividerMap.map { case (sink, division) =>
+      val requested = sink.take.get.freqMHz
+      val actual = referenceFreqMHz / division.toDouble
+      s"  Output clock ${sink.name.get}, requested: ${requested} MHz, actual: ${actual} MHz (division of ${division})"
+    }
+    println(preamble + outputSummaries.mkString("\n"))
+  }
+}
+
 case class IdealizedPLLNode(pllName: String)(implicit valName: ValName)
   extends MixedNexusNode(ClockImp, ClockGroupImp)(
     dFn = { _ => ClockGroupSourceParameters() },
@@ -53,9 +71,8 @@ class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) ex
     val (outClocks, ClockGroupEdgeParameters(_, outSinkParams,  _, _)) = node.out.head
 
     val referenceFreq = refSinkParam.take.get.freqMHz
-    println(s"Idealized PLL Frequency Summary")
-    println(s"-------------------------------")
-    println(s"  Requested Reference Frequency: ${referenceFreq} MHz")
+    val pllConfig = new SimplePllConfiguration(outSinkParams.members)
+    pllConfig.prettyPrint(pllName)
 
     val dividedClocks = mutable.HashMap[Int, Clock]()
     def instantiateDivider(div: Int): Clock = {
@@ -67,10 +84,7 @@ class IdealizedPLL(pllName: String)(implicit p: Parameters, valName: ValName) ex
     }
 
     for (((sinkBName, sinkB), sinkP) <- outClocks.member.elements.zip(outSinkParams.members)) {
-      val requested = sinkP.take.get.freqMHz
-      val div = Math.round(referenceFreq / requested).toInt
-      val actual = referenceFreq / div.toDouble
-      println(s"  Output Clock ${sinkBName}: Requested: ${requested} MHz, Actual: ${actual} MHz (division of ${div})")
+      val div = pllConfig.sinkDividerMap(sinkP)
       sinkB.clock := dividedClocks.getOrElse(div, instantiateDivider(div))
       sinkB.reset := refClock.reset
     }