From 96e838c773c8a32de55f0636ee46bc5d7e73e556 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 17 May 2020 00:18:54 +0000 Subject: [PATCH] [firechip] Set the cover property library in FireSim Harnesses --- generators/firechip/src/main/scala/FireSim.scala | 1 + generators/firechip/src/main/scala/FireSimMulticlockPOC.scala | 1 + 2 files changed, 2 insertions(+) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 50f6f658..a4cea5ec 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -29,6 +29,7 @@ object NodeIdx { } class FireSim(implicit val p: Parameters) extends RawModule { + freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) val clockBridge = Module(new RationalClockBridge) val clock = clockBridge.io.clocks.head val reset = WireInit(false.B) diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index 758cb055..1f1ae06a 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -84,6 +84,7 @@ class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.Digita // Harness Definition class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { + freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) val refClock = clockBridge.io.clocks.head val reset = WireInit(false.B)