From 984ea24650e0308783819e7fd334c3a0ac555ca2 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 5 Jul 2023 14:55:03 -0700 Subject: [PATCH] Apply suggestions from code review Co-authored-by: Abraham Gonzalez --- .../chipyard/src/main/scala/clocking/HasChipyardPRCI.scala | 4 ++-- .../chipyard/src/main/scala/config/AbstractConfig.scala | 4 ++-- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 2 +- .../{MultiHarnesBinders.scala => MultiHarnessBinders.scala} | 0 4 files changed, 5 insertions(+), 5 deletions(-) rename generators/chipyard/src/main/scala/harness/{MultiHarnesBinders.scala => MultiHarnessBinders.scala} (100%) diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 5fb8f6ef..906a631d 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -21,7 +21,7 @@ case class ChipyardPRCIControlParams( baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, - enableResetSynchronizers: Boolean = true // this should only be disable to work around verilator async-reset initialziation problems + enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating || enableTileResetSetting } @@ -110,7 +110,7 @@ PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN -RTL SIMULATORS. +RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 218b435c..80b59efe 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -22,7 +22,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present - new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port + new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port new chipyard.harness.WithClockAndResetFromHarness ++ // all Clock/Reset I/O in ChipTop should be driven by harnessClockInstantiator new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz @@ -35,7 +35,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithSPIIOCells ++ new chipyard.iobinders.WithExtInterruptIOCells ++ new chipyard.iobinders.WithCustomBootPin ++ - // The "punchtrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO + // The "punchthrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO // Instead, they directly pass through the DigitalTop ports to ports in the ChipTop new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithAXI4MMIOPunchthrough ++ diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index c1e641b0..f4bee2af 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -60,7 +60,7 @@ class ChipBringupHostConfig extends Config( new testchipip.WithSerialTLWidth(4) ++ // match width with the chip new testchipip.WithSerialTLMem(base = 0x0, size = 0x80000000L, // accessible memory of the chip that doesn't come from the tethered host idBits = 4, isMainMemory = false) ++ // This assumes off-chip mem starts at 0x8000_0000 - new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 50MHz clock + new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock //============================ // Setup bus topology on the bringup system diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnesBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala similarity index 100% rename from generators/chipyard/src/main/scala/harness/MultiHarnesBinders.scala rename to generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala