From c9c166f4a6c234fb1ff7aa3971784d7ae101c41b Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 30 Aug 2019 01:27:14 -0700 Subject: [PATCH] comment on the sim_* variables --- common.mk | 4 ++-- variables.mk | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index 16208e82..d920cf4d 100644 --- a/common.mk +++ b/common.mk @@ -31,7 +31,7 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala) touch $@ ######################################################################################### -# create simulation args file rule +# create list of simulation file inputs ######################################################################################### $(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" @@ -65,7 +65,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" ######################################################################################## -# remove duplicate files in blackbox/simfiles +# remove duplicate files and headers in list of simulation file inputs ######################################################################################## $(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes) awk '{print $1;}' $^ | sort -u | grep -v '.*\.h' > $@ diff --git a/variables.mk b/variables.mk index 41d5ef81..6a0c5e1b 100644 --- a/variables.mk +++ b/variables.mk @@ -113,9 +113,11 @@ HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir +# files that contain lists of files needed for VCS or Verilator simulation sim_files ?= $(build_dir)/sim_files.f sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f +# single file that contains all files needed for VCS or Verilator simulation (unique and without .h's) sim_common_files ?= $(build_dir)/sim_files.common.f #########################################################################################