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Address some docs, build.sbt, .gitmodules

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abejgonzalez
2020-11-12 15:31:34 -08:00
parent d5a0fd1a8e
commit 999ae05bfe
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2
docs/Chipyard-Basics/Chipyard-Components.rst
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@@ -130,7 +130,7 @@ Prototyping
**FPGA Prototyping**
FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``.
Some examples of FPGAs supported are the Xilinx Arty 35T and VCU118 boards.
To instead do an fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform.
For a fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`FireSim` platform.
See :ref:`Prototyping Flow` for more information on FPGA prototypes.
VLSI

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docs/Prototyping/General.rst
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@@ -4,7 +4,7 @@ General Setup and Usage
Sources and Submodule Setup
---------------------------
All FPGA related collateral and sources are located in the ``fpga`` top-level Chipyard directory.
All FPGA prototyping-related collateral and sources are located in the ``fpga`` top-level Chipyard directory.
This includes the ``fpga-shells`` submodule and the ``src`` directory that hold both Scala, TCL and other collateral.
However, the ``fpga-shells`` submodule repository is not initialized by default.
To initialize the ``fpga-shells`` submodule repository, run the included initialization script from the Chipyard top-level directory:
@@ -22,22 +22,22 @@ Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you c
.. code-block:: shell
make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... bit
make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... BOARD=... bitstream
# or
make SUB_PROJECT=<sub_project> bit
make SUB_PROJECT=<sub_project> bitstream
The ``SUB_PROJECT`` make variable is a way to meta make variable that sets all of the other make variables to a specific default.
For example:
.. code-block:: shell
make SUB_PROJECT=vcu118 bit
make SUB_PROJECT=vcu118 bitstream
# converts to
make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 bit
make SBT_PROJECT=fpga_platforms MODEL=VCU118FPGATestHarness VLOG_MODEL=VCU118FPGATestHarness MODEL_PACKAGE=chipyard.fpga.vcu118 CONFIG=RocketVCU118Config CONFIG_PACKAGE=chipyard.fpga.vcu118 GENERATOR_PACKAGE=chipyard TB=none TOP=ChipTop BOARD=vcu118 bitstream
Some ``SUB_PROJECT`` defaults are already defined for use, including ``vcu118`` and ``arty``.
These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more for the Chipyard make system.
@@ -47,22 +47,24 @@ For example, building the BOOM configuration on the VCU118:
.. code-block:: shell
make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bit
make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bitstream
That command will build the RTL and generate a bitstream using Vivado.
The generated bitstream will be located in your designs specific build folder (``generated-src/<LONG_NAME>/obj``).
However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL.
Debugging with ILAs on Supported FPGAs
--------------------------------------
Adding an ILA (integrated logic analyzer) can be added to certain designs for debugging relevant signals.
ILA (integrated logic analyzers) can be added to certain designs for debugging relevant signals.
First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``).
Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA).
This can be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``.
This will create a new bitstream called ``debug_output`` in the same location as the normal bitstream (``generated-src/<LONG_NAME>/obj``).
For example, running the bitstream build for an added ILA for a BOOM config.:
.. code-block:: shell
make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream
For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform.
.. IMPORTANT:: For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform.

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docs/Prototyping/VCU118.rst
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@@ -4,10 +4,10 @@ Running a Design on VCU118
Basic Design
------------
The default VCU118 FPGA target design is setup to have UART, a SPI SDCard, and DDR backing memory.
The default Xilinx VCU118 harness is setup to have UART, a SPI SDCard, and DDR backing memory.
This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118).
To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``.
Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config.
Adding this config fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config.
.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala
:language: scala
@@ -50,6 +50,6 @@ For more information on harness binders and io binders, refer to :ref:`IOBinders
An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``.
This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port.
.. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation.
For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``.
.. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation.
For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``.
See :ref:`Making a Bitstream` for information on the various make variables.

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docs/Prototyping/index.rst
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@@ -3,7 +3,6 @@ Prototyping Flow
Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells <https://github.com/sifive/fpga-shells>`__.
This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty 35T board.
FPGA prototyping allows for orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times and less design introspection.
.. Note:: While ``fpga-shells`` provides harnesses for other FPGA development boards such as the Xilinx VC707 and some MicroSemi PolarFire, only harnesses for the Xilinx VCU118 and Xilinx Arty 35T boards are currently supported in Chipyard.
However, the VCU118 and Arty 35T examples demonstrate how a user may implement support for other harnesses provided by fpga-shells.