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Use Chipyard configs as a base (VCU118)

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abejgonzalez
2020-11-05 20:30:49 -08:00
parent 083f34ab23
commit 9a5b67bf8c
4 changed files with 21 additions and 24 deletions
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28
fpga/src/main/scala/vcu118/Configs.scala
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@@ -15,6 +15,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import testchipip.{SerialTLKey}
import chipyard.{BuildSystem} import chipyard.{BuildSystem}
class WithDefaultPeripherals extends Config((site, here, up) => { class WithDefaultPeripherals extends Config((site, here, up) => {
@@ -45,10 +47,11 @@ class WithSystemModifications extends Config((site, here, up) => {
require (make.! == 0, "Failed to build bootrom") require (make.! == 0, "Failed to build bootrom")
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
} }
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size
case SerialTLKey => None // remove serialized tl port
}) })
class AbstractVCU118Config extends Config( class WithVCU118Tweaks extends Config(
new WithUART ++ new WithUART ++
new WithSPISDCard ++ new WithSPISDCard ++
new WithDDRMem ++ new WithDDRMem ++
@@ -56,27 +59,18 @@ class AbstractVCU118Config extends Config(
new WithSPIIOPassthrough ++ new WithSPIIOPassthrough ++
new WithTLIOPassthrough ++ new WithTLIOPassthrough ++
new WithDefaultPeripherals ++ new WithDefaultPeripherals ++
new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top
new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new chipyard.config.WithNoSubsystemDrivenClocks ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1))
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new chipyard.WithMulticlockCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class RocketVCU118Config extends Config( class RocketVCU118Config extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new WithVCU118Tweaks ++
new AbstractVCU118Config) new chipyard.RocketConfig)
class BoomVCU118Config extends Config( class BoomVCU118Config extends Config(
new WithFPGAFrequency(75) ++ new WithFPGAFrequency(75) ++
new boom.common.WithNLargeBooms(1) ++ new WithVCU118Tweaks ++
new AbstractVCU118Config) new chipyard.MegaBoomConfig)
class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => { class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => {
case FPGAFrequencyKey => MHz case FPGAFrequencyKey => MHz

13
fpga/src/main/scala/vcu118/bringup/Configs.scala
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@@ -15,7 +15,7 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import chipyard.{BuildSystem} import chipyard.{BuildSystem}
import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config} import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency}
class WithBringupPeripherals extends Config((site, here, up) => { class WithBringupPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L)))
@@ -51,9 +51,12 @@ class WithBringupAdditions extends Config(
new WithBringupVCU118System) new WithBringupVCU118System)
class RocketBringupConfig extends Config( class RocketBringupConfig extends Config(
new WithBringupPeripherals ++ new WithBringupAdditions ++
new RocketVCU118Config) new WithVCU118Tweaks ++
new chipyard.RocketConfig)
class BoomBringupConfig extends Config( class BoomBringupConfig extends Config(
new WithBringupPeripherals ++ new WithFPGAFrequency(75) ++
new BoomVCU118Config) new WithBringupAdditions ++
new WithVCU118Tweaks ++
new chipyard.MegaBoomConfig)

2
fpga/src/main/scala/vcu118/bringup/TestHarness.scala
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@@ -68,5 +68,5 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
} }
class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) { class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) {
val bringupOuter = _outer lazy val bringupOuter = _outer
} }