From 9ab9132c8b30753450518f9ca3f4ab03719b3b92 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Thu, 4 Jan 2024 13:34:53 -0800
Subject: [PATCH] Fix missing childClock/childReset in Arty100THarness

---
 fpga/src/main/scala/arty100t/Harness.scala | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala
index 577bd1b2..30a382e1 100644
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -76,6 +76,9 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
     def referenceReset = dutClock.in.head._1.reset
     def success = { require(false, "Unused"); false.B }
 
+    childClock := harnessBinderClock
+    childReset := harnessBinderReset
+
     ddrOverlay.mig.module.clock := harnessBinderClock
     ddrOverlay.mig.module.reset := harnessBinderReset
     ddrBlockDuringReset.module.clock := harnessBinderClock