diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 9a34b198..f0dd91cc 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -6,7 +6,7 @@ import freechips.rocketchip.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet} +import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} import freechips.rocketchip.system._ import freechips.rocketchip.tile._ @@ -20,7 +20,6 @@ import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} import chipyard.{BuildTop} -import chipyard.fpga.vcu118.bringup.{BringupGPIOs} import chipyard.harness._ @@ -29,7 +28,12 @@ class WithBringupPeripherals extends Config((site, here, up) => { UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L)), + SPIParams(rAddress = BigInt(0x64001000L), + injectFunc = Some((spi: TLSPI) => { + ResourceBinding { + Resource(new MMCDevice(spi.device, 1), "reg").bind(ResourceAddress(0)) + } + })), SPIParams(rAddress = BigInt(0x64004000L))) case VCU118ShellPMOD => "SDIO" case PeripheryI2CKey => List( diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index d10f5500..ece212bb 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -59,18 +59,6 @@ class WithSPIIOPassthrough extends OverrideIOBinder({ } }) -//class WithMMCSPIDTS extends OverrideIOBinder({ -// (system: HasPeripherySPI) => { -// -// val mmcDev = new MMCDevice(system.tlspi.head.device, 1) -// ResourceBinding { -// Resource(mmcDev, "reg").bind(ResourceAddress(0)) -// } -// -// (Nil, Nil) -// } -//}) - class WithI2CIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryI2CModuleImp) => { val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") } diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 413e0a88..ed9f63f9 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 413e0a88a4e48b1966b9444d613a7f3a776e65aa +Subproject commit ed9f63f9f5b9209c9e5ef2adfd063d6669691d79