From 9ed41fc3dca9d1eae83521dc70b29e1edb00a6aa Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 7 Feb 2017 17:33:38 -0800
Subject: [PATCH] fully switch to chisel3

---
 rocket-chip                              |  2 +-
 src/main/scala/example/TestHarness.scala |  8 +++----
 src/main/scala/pwm/PWM.scala             | 30 ++++++++++++------------
 testchipip                               |  2 +-
 4 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/rocket-chip b/rocket-chip
index f5a8ba28..f3299ae9 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit f5a8ba280d37549b437287b7548660bd783923ee
+Subproject commit f3299ae91d3f01d0349eb4746886e303e8fb1b41
diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala
index 7d2348e2..a6d8c290 100644
--- a/src/main/scala/example/TestHarness.scala
+++ b/src/main/scala/example/TestHarness.scala
@@ -4,13 +4,13 @@ import util.GeneratorApp
 import diplomacy.LazyModule
 import rocketchip._
 import testchipip._
-import Chisel._
+import chisel3._
 import cde.Parameters
 
 class TestHarness(implicit val p: Parameters) extends Module {
-  val io = new Bundle {
-    val success = Bool(OUTPUT)
-  }
+  val io = IO(new Bundle {
+    val success = Output(Bool())
+  })
 
   def buildTop(p: Parameters): ExampleTop = LazyModule(new ExampleTop(p))
 
diff --git a/src/main/scala/pwm/PWM.scala b/src/main/scala/pwm/PWM.scala
index c857c7a4..9defa16d 100644
--- a/src/main/scala/pwm/PWM.scala
+++ b/src/main/scala/pwm/PWM.scala
@@ -9,12 +9,12 @@ import diplomacy._
 import rocketchip._
 
 class PWMBase extends Module {
-  val io = new Bundle {
-    val pwmout = Bool(OUTPUT)
-    val period = UInt(INPUT, 64)
-    val duty = UInt(INPUT, 64)
-    val enable = Bool(INPUT)
-  }
+  val io = IO(new Bundle {
+    val pwmout = Output(Bool())
+    val period = Input(UInt(64.W))
+    val duty = Input(UInt(64.W))
+    val enable = Input(Bool())
+  })
 
   // The counter should count up until period is reached
   val counter = Reg(UInt(width = 64))
@@ -31,10 +31,10 @@ class PWMBase extends Module {
 }
 
 class PWMTL(implicit p: Parameters) extends Module {
-  val io = new Bundle {
-    val pwmout = Bool(OUTPUT)
-    val tl = new ClientUncachedTileLinkIO().flip
-  }
+  val io = IO(new Bundle {
+    val pwmout = Output(Bool())
+    val tl = Flipped(new ClientUncachedTileLinkIO())
+  })
 
   // How many clock cycles in a PWM cycle?
   val period = Reg(UInt(width = 64))
@@ -95,10 +95,10 @@ class PWMTL(implicit p: Parameters) extends Module {
 }
 
 class PWMAXI(implicit p: Parameters) extends Module {
-  val io = new Bundle {
-    val pwmout = Bool(OUTPUT)
-    val axi = new NastiIO().flip
-  }
+  val io = IO(new Bundle {
+    val pwmout = Output(Bool())
+    val axi = Flipped(new NastiIO())
+  })
 
   // How many clock cycles in a PWM cycle?
   val period = Reg(UInt(width = 64))
@@ -158,7 +158,7 @@ trait PeripheryPWM extends LazyModule {
 }
 
 trait PeripheryPWMBundle {
-  val pwmout = Bool(OUTPUT)
+  val pwmout = Output(Bool())
 }
 
 case object BuildPWM extends Field[(ClientUncachedTileLinkIO, Parameters) => Bool]
diff --git a/testchipip b/testchipip
index 63bf0939..69b66e4b 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 63bf093975d3bcd349fea5ae7e349939c6f95fca
+Subproject commit 69b66e4b1d893672d3c6f2fa3797394f391c096c