From a02700a1d4a39d433b2e3a2b0bdfad176d9375ed Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 18 Sep 2020 23:14:47 -0700 Subject: [PATCH] Add documentation for sodor --- docs/Generators/Sodor.rst | 17 +++++++++++++++++ docs/Generators/index.rst | 1 + generators/riscv-sodor | 2 +- 3 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 docs/Generators/Sodor.rst diff --git a/docs/Generators/Sodor.rst b/docs/Generators/Sodor.rst new file mode 100644 index 00000000..7f4282eb --- /dev/null +++ b/docs/Generators/Sodor.rst @@ -0,0 +1,17 @@ +Sodor Core +==================================== + +`Sodor `__ is a collection of 5 simple RV32MI cores designed for educational purpose. +The `Sodor core` is wrapped in an tile during generation so it can be used as a component within the `Rocket Chip SoC generator`. +The cores contain a small scratchpad memory to which the program are loaded through a TileLink slave port, and the cores **DO NOT** +support external memory. + +The five available cores and their corresponding generator configuration are: + +* 1-stage (essentially an ISA simulator) - ``Sodor1StageConfig`` +* 2-stage (demonstrates pipelining in Chisel) - ``Sodor2StageConfig`` +* 3-stage (uses sequential memory; supports both Harvard (``Sodor3StageConfig``) and Princeton (``Sodor3StageSinglePortConfig``) versions) +* 5-stage (can toggle between fully bypassed or fully interlocked) - ``Sodor5StageConfig`` +* "bus"-based micro-coded implementation - ``SodorUCodeConfig`` + +For more information, please refer to the `GitHub repository `__. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index be9c5e55..cebb17e5 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -29,4 +29,5 @@ so changes to the generators themselves will automatically be used when building SHA3 Ariane NVDLA + Sodor diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 69df2b01..12fa11e4 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 69df2b013f162cf4c450cdc3e7bbd6e7b9f2de16 +Subproject commit 12fa11e485c4854a48eec0561698dd0b32230243