From a146d0040d4112c4b4fbe253b235481d546b4337 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 19 Aug 2019 11:15:07 -0700 Subject: [PATCH] [firechip] Add MIDAS environments for all targets --- .../firechip/src/main/scala/SimConfigs.scala | 16 +-------- .../src/main/scala/TargetConfigs.scala | 36 +++++++++++++++++-- .../firechip/src/main/scala/Targets.scala | 34 ++++++++++++------ 3 files changed, 59 insertions(+), 27 deletions(-) diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala index 937c2877..6f6464dc 100644 --- a/generators/firechip/src/main/scala/SimConfigs.scala +++ b/generators/firechip/src/main/scala/SimConfigs.scala @@ -19,40 +19,26 @@ import firesim.configs._ * reconstruct what is in a particular AGFI. These tags are also used to * determine which driver to build. *******************************************************************************/ -class FireSimConfig extends Config( - new WithSerialWidget ++ - new WithUARTWidget ++ - new WithSimpleNICWidget ++ - new WithBlockDevWidget ++ - new WithDefaultMemModel ++ - new WithTracerVWidget ++ - new BasePlatformConfig) +class FireSimConfig extends Config(new BasePlatformConfig) class FireSimClockDivConfig extends Config( - new WithDefaultMemModel(clockDivision = 2) ++ new FireSimConfig) class FireSimDDR3Config extends Config( - new FCFS16GBQuadRank ++ new FireSimConfig) class FireSimDDR3LLC4MBConfig extends Config( - new FCFS16GBQuadRankLLC4MB ++ new FireSimConfig) class FireSimDDR3FRFCFSConfig extends Config( - new FRFCFS16GBQuadRank ++ new FireSimConfig) class FireSimDDR3FRFCFSLLC4MBConfig extends Config( - new FRFCFS16GBQuadRankLLC4MB ++ new FireSimConfig) class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config( - new FRFCFS16GBQuadRankLLC4MB3Div ++ new FireSimConfig) class Midas2Config extends Config( new WithMultiCycleRamModels ++ new FireSimConfig) - diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 9be95d89..531c067a 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -10,10 +10,14 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.DebugModuleParams import boom.system.BoomTilesKey -import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig} +import testchipip.{BlockDeviceKey, BlockDeviceConfig} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import icenet._ +import firesim.util.{EndpointKey, TieOffDebug} +import firesim.endpoints._ +import firesim.configs.WithDefaultMemModel + class WithBootROM extends Config((site, here, up) => { case BootROMParams => { val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") @@ -33,13 +37,33 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => }) class WithUARTKey extends Config((site, here, up) => { - case PeripheryUARTKey => List(UARTParams( + case EndpointKey => up(EndpointKey) ++ Seq(UARTEndpoint) + case PeripheryUARTKey => List(UARTParams( address = BigInt(0x54000000L), nTxEntries = 256, nRxEntries = 256)) }) +class WithSerialEndpoint extends Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(SerialEndpoint) +}) + +class WithTracerVEndpoint extends Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(TracerVEndpoint) +}) + +class WithBlockDevice extends Config( + new Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(BlockDevEndpoint, firesim.util.FASEDEndpointMatcher) + }) ++ new testchipip.WithBlockDevice +) + +class WithTieOffDebug extends Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(TieOffDebug) +}) + class WithNICKey extends Config((site, here, up) => { + //case EndpointKey => up(EndpointKey) ++ Seq(NICEndpoint) case NICKey => NICConfig( inBufFlits = 8192, ctrlQueueDepth = 64) @@ -97,6 +121,10 @@ class FireSimRocketChipConfig extends Config( new WithRocketL2TLBs(1024) ++ new WithPerfCounters ++ new WithoutClockGating ++ + new WithDefaultMemModel ++ + new WithSerialEndpoint ++ + new WithTracerVEndpoint ++ + new WithTieOffDebug ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -136,6 +164,10 @@ class FireSimBoomConfig extends Config( new WithBlockDevice ++ new WithBoomL2TLBs(1024) ++ new WithoutClockGating ++ + new WithDefaultMemModel ++ + new WithSerialEndpoint ++ + new WithTracerVEndpoint ++ + new WithTieOffDebug ++ // Using a small config because it has 64-bit system bus, and compiles quickly new boom.system.SmallBoomConfig) diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 34477509..e592f5d1 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -17,8 +17,14 @@ import testchipip._ import testchipip.SerialAdapter.SERIAL_IF_WIDTH import sifive.blocks.devices.uart._ import midas.models.AXI4BundleWithEdge +import firesim.util.IOMatchingMIDASEnvironment import java.io.File + +object FireSimValName { + implicit val valName = ValName("TestHarness") +} +import FireSimValName._ /******************************************************************************* * Top level DESIGN configurations. These describe the basic instantiations of * the designs being simulated. @@ -30,7 +36,7 @@ import java.io.File * determine which driver to build. *******************************************************************************/ -class FireSim(implicit p: Parameters) extends RocketSubsystem +class FireSimDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -44,7 +50,7 @@ class FireSim(implicit p: Parameters) extends RocketSubsystem override lazy val module = new FireSimModuleImp(this) } -class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) +class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -56,8 +62,9 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) with HasTraceIOImp with CanHaveRocketMultiCycleRegfileImp +class FireSim(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimDUT).module) -class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem +class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -70,7 +77,7 @@ class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem override lazy val module = new FireSimNoNICModuleImp(this) } -class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemModuleImp(l) +class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -82,7 +89,9 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod with CanHaveRocketMultiCycleRegfileImp -class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem +class FireSimNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimNoNICDUT).module) + +class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -96,7 +105,7 @@ class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem override lazy val module = new FireBoomModuleImp(this) } -class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleImp(l) +class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -109,7 +118,9 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp -class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem +class FireBoom(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomDUT).module) + +class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -122,7 +133,7 @@ class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem override lazy val module = new FireBoomNoNICModuleImp(this) } -class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsystemModuleImp(l) +class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -134,6 +145,8 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsys with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp +class FireBoomNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomNoNICDUT).module) + case object NumNodes extends Field[Int] class SupernodeIO( @@ -152,10 +165,10 @@ class SupernodeIO( } -class FireSimSupernode(implicit p: Parameters) extends Module { +class FireSimSupernodeDUT(implicit p: Parameters) extends Module { val nNodes = p(NumNodes) val nodes = Seq.fill(nNodes) { - Module(LazyModule(new FireSim).module) + Module(LazyModule(new FireSimDUT).module) } val io = IO(new SupernodeIO(nNodes, SERIAL_IF_WIDTH, nodes(0).mem_axi4.get)) @@ -178,3 +191,4 @@ class FireSimSupernode(implicit p: Parameters) extends Module { } } } +class FireSimSupernode(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => new FireSimSupernodeDUT)