diff --git a/src/main/scala/pwm/PWM.scala b/src/main/scala/pwm/PWM.scala
index 6fe9aced..8083b078 100644
--- a/src/main/scala/pwm/PWM.scala
+++ b/src/main/scala/pwm/PWM.scala
@@ -52,7 +52,7 @@ trait PWMTLModule extends Module with HasRegMap {
   // For how many cycles should the clock be high?
   val duty = Reg(UInt(w.W))
   // Is the PWM even running at all?
-  val enable = Reg(init = false.B)
+  val enable = RegInit(false.B)
 
   val base = Module(new PWMBase(w))
   io.pwmout := base.io.pwmout
diff --git a/testchipip b/testchipip
index 27f0aed7..82db791a 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit 27f0aed7b6b57d0621081b2638569775f9a530fc
+Subproject commit 82db791a5fa923604dc622673fddfb6bade9d24e