From a27bc7f5ede753f05a742184fe779ca523a57693 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 10 Mar 2024 12:16:12 -0700 Subject: [PATCH] Bump rocket-chip to standalone diplomacy --- .github/scripts/check-commit.sh | 2 +- .gitmodules | 3 ++ build.sbt | 16 +++++++- fpga/fpga-shells | 2 +- fpga/src/main/scala/arty/HarnessBinders.scala | 2 +- fpga/src/main/scala/arty100t/Configs.scala | 3 +- .../main/scala/arty100t/HarnessBinders.scala | 5 +-- fpga/src/main/scala/nexysvideo/Configs.scala | 2 +- .../scala/nexysvideo/HarnessBinders.scala | 1 + .../src/main/scala/vc707/HarnessBinders.scala | 4 +- .../main/scala/vcu118/HarnessBinders.scala | 4 +- .../chipyard/src/main/scala/DigitalTop.scala | 8 +--- .../chipyard/src/main/scala/Subsystem.scala | 4 +- .../chipyard/src/main/scala/System.scala | 19 ++++----- .../main/scala/example/CustomChipTop.scala | 4 +- .../src/main/scala/example/FlatChipTop.scala | 2 +- .../chipyard/src/main/scala/example/GCD.scala | 4 +- .../src/main/scala/example/InitZero.scala | 3 +- .../scala/example/dsptools/GenericFIR.scala | 1 + .../dsptools/StreamingPassthrough.scala | 1 + .../src/main/scala/iobinders/IOBinders.scala | 40 +++++++++++-------- .../src/main/scala/iobinders/Ports.scala | 2 +- generators/diplomacy | 1 + generators/fft-generator | 2 +- generators/nvdla | 2 +- generators/rocc-acc-utils | 2 +- generators/rocket-chip | 2 +- generators/rocket-chip-blocks | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/System.scala | 2 +- sims/firesim | 2 +- tools/rocket-dsp-utils | 2 +- 32 files changed, 88 insertions(+), 63 deletions(-) create mode 160000 generators/diplomacy diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh index a4a95611..8043c12f 100755 --- a/.github/scripts/check-commit.sh +++ b/.github/scripts/check-commit.sh @@ -45,7 +45,7 @@ search () { done } -submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils") +submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy") dir="generators" branches=("master" "main" "dev") search diff --git a/.gitmodules b/.gitmodules index 2783bf9b..6ebbad59 100644 --- a/.gitmodules +++ b/.gitmodules @@ -16,6 +16,9 @@ [submodule "generators/cva6"] path = generators/cva6 url = https://github.com/ucb-bar/cva6-wrapper.git +[submodule "generators/diplomacy"] + path = generators/diplomacy + url = https://github.com/chipsalliance/diplomacy.git [submodule "generators/fft-generator"] path = generators/fft-generator url = https://github.com/ucb-bar/FFTGenerator.git diff --git a/build.sbt b/build.sbt index 2288cded..d929b3ca 100644 --- a/build.sbt +++ b/build.sbt @@ -113,8 +113,19 @@ lazy val rocketMacros = (project in rocketChipDir / "macros") ) ) +lazy val diplomacy = freshProject("diplomacy", file("generators/diplomacy/diplomacy")) + .dependsOn(cde) + .settings(commonSettings) + .settings(chiselSettings) + .settings(Compile / scalaSource := baseDirectory.value / "diplomacy") + .settings( + libraryDependencies ++= Seq( + "com.lihaoyi" %% "sourcecode" % "0.3.1" + ) + ) + lazy val rocketchip = freshProject("rocketchip", rocketChipDir) - .dependsOn(hardfloat, rocketMacros, cde) + .dependsOn(hardfloat, rocketMacros, diplomacy, cde) .settings(commonSettings) .settings(chiselSettings) .settings( @@ -123,7 +134,8 @@ lazy val rocketchip = freshProject("rocketchip", rocketChipDir) "org.scala-lang" % "scala-reflect" % scalaVersion.value, "org.json4s" %% "json4s-jackson" % "4.0.5", "org.scalatest" %% "scalatest" % "3.2.0" % "test", - "org.scala-graph" %% "graph-core" % "1.13.5" + "org.scala-graph" %% "graph-core" % "1.13.5", + "com.lihaoyi" %% "sourcecode" % "0.3.1" ) ) .settings( // Settings for scalafix diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 93004b7b..6019bb35 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 93004b7bd02eb7cc32a25cc1bc40595b93add118 +Subproject commit 6019bb3508d12887b01765f3cad512c3282aeb70 diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 39ddd204..fcc07758 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -5,7 +5,7 @@ import chisel3._ import freechips.rocketchip.devices.debug.{HasPeripheryDebug} import freechips.rocketchip.jtag.{JTAGIO} -import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp} +import sifive.blocks.devices.uart.{UARTPortIO} import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort} import sifive.blocks.devices.pinctrl.{BasePin} diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala index f64dbdf3..9d945824 100644 --- a/fpga/src/main/scala/arty100t/Configs.scala +++ b/fpga/src/main/scala/arty100t/Configs.scala @@ -5,7 +5,8 @@ import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.system._ import freechips.rocketchip.tile._ diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala index c2b89a24..35b3c3b1 100644 --- a/fpga/src/main/scala/arty100t/HarnessBinders.scala +++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala @@ -5,10 +5,9 @@ import chisel3._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem.{PeripheryBusKey} import freechips.rocketchip.tilelink.{TLBundle} -import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.diplomacy.{LazyRawModuleImp} - -import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams} +import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag} +import sifive.blocks.devices.uart.{UARTPortIO, UARTParams} import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort} import sifive.blocks.devices.pinctrl.{BasePin} import sifive.fpgashells.shell._ diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala index ce8fbae8..2aa241c7 100644 --- a/fpga/src/main/scala/nexysvideo/Configs.scala +++ b/fpga/src/main/scala/nexysvideo/Configs.scala @@ -5,7 +5,7 @@ import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.debug._ import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.system._ import freechips.rocketchip.tile._ diff --git a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala index 29deeadb..722971a1 100644 --- a/fpga/src/main/scala/nexysvideo/HarnessBinders.scala +++ b/fpga/src/main/scala/nexysvideo/HarnessBinders.scala @@ -7,6 +7,7 @@ import freechips.rocketchip.subsystem.{PeripheryBusKey} import freechips.rocketchip.tilelink.{TLBundle} import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.diplomacy.{LazyRawModuleImp} +import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag} import sifive.blocks.devices.uart.{UARTParams} diff --git a/fpga/src/main/scala/vc707/HarnessBinders.scala b/fpga/src/main/scala/vc707/HarnessBinders.scala index d08fba76..b872f08a 100644 --- a/fpga/src/main/scala/vc707/HarnessBinders.scala +++ b/fpga/src/main/scala/vc707/HarnessBinders.scala @@ -3,10 +3,10 @@ package chipyard.fpga.vc707 import chisel3._ import chisel3.experimental.{BaseModule} -import freechips.rocketchip.util.{HeterogeneousBag} +import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag} import freechips.rocketchip.tilelink.{TLBundle} -import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} +import sifive.blocks.devices.uart.{UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{HasSystemXilinxVC707PCIeX1ModuleImp, XilinxVC707PCIeX1IO} diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index a4b52c63..6b977531 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -3,10 +3,10 @@ package chipyard.fpga.vcu118 import chisel3._ import chisel3.experimental.{BaseModule} -import freechips.rocketchip.util.{HeterogeneousBag} +import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag} import freechips.rocketchip.tilelink.{TLBundle} -import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO} +import sifive.blocks.devices.uart.{UARTPortIO} import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO} import chipyard._ diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index ae0c8dad..e0f69392 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -43,12 +43,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem override lazy val module = new DigitalTopModule(this) } -class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) - with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp - with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp - with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp - with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp - with sifive.blocks.devices.spi.HasPeripherySPIModuleImp +class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l) with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 7629cf83..49d4b2f6 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -121,6 +121,6 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem } class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) - with HasHierarchicalElementsRootContextModuleImp -{ + with HasHierarchicalElementsRootContextModuleImp { + override lazy val outer = _outer } diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index b8a04eac..d67f99bd 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -38,7 +38,7 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem /** * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem */ -class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer) +class ChipyardSystemModule(_outer: ChipyardSystem) extends ChipyardSubsystemModuleImp(_outer) with HasRTCModuleImp with HasExtInterruptsModuleImp with DontTouch @@ -60,6 +60,7 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem => private val portName = "tl_mem" private val device = new MemoryDevice private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1) + private val mbus = tlBusWrapperLocationMap.lift(MBUS).getOrElse(locateTLBusWrapper(SBUS)) val memTLNode = TLManagerNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) => Seq.tabulate(nMemoryChannels) { channel => @@ -76,15 +77,15 @@ trait CanHaveMasterTLMemPort { this: BaseSubsystem => supportsPutFull = TransferSizes(1, mbus.blockBytes), supportsPutPartial = TransferSizes(1, mbus.blockBytes))), beatBytes = memPortParams.beatBytes) - } - }).toList.flatten) + } + }).toList.flatten) - mbus.coupleTo(s"memory_controller_port_named_$portName") { - (memTLNode - :*= TLBuffer() - :*= TLSourceShrinker(1 << idBits) - :*= TLWidthWidget(mbus.beatBytes) - :*= _) + mbus.coupleTo(s"memory_controller_port_named_$portName") { + (memTLNode + :*= TLBuffer() + :*= TLSourceShrinker(1 << idBits) + :*= TLWidthWidget(mbus.beatBytes) + :*= _) } val mem_tl = InModuleBody { memTLNode.makeIOs() } diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala index f710ccab..eb0565ce 100644 --- a/generators/chipyard/src/main/scala/example/CustomChipTop.scala +++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala @@ -67,13 +67,13 @@ class WithCustomChipTop extends Config((site, here, up) => { }) class WithBrokenOutUARTIO extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => { + (system: HasPeripheryUART) => { val uart_txd = IO(Output(Bool())) val uart_rxd = IO(Input(Bool())) system.uart(0).rxd := uart_rxd uart_txd := system.uart(0).txd val where = PBUS // TODO fix - val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where) + val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where) val freqMHz = bus.dtsFrequency.get / 1000000 (Seq(UARTPort(() => { val uart_wire = Wire(new UARTPortIO(system.uart(0).c)) diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index d4caa49b..6b249286 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -145,7 +145,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor // UART //========================== require(system.uarts.size == 1) - val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey)) + val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.uart.head, "uart_0", p(IOCellKey)) val where = PBUS // TODO fix val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where) val freqMHz = bus.dtsFrequency.get / 1000000 diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index ef3edc1f..7fdb1714 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -5,7 +5,7 @@ import chisel3.util._ import chisel3.experimental.{IntParam, BaseModule} import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.prci._ -import freechips.rocketchip.subsystem.BaseSubsystem +import freechips.rocketchip.subsystem.{BaseSubsystem, PBUS} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper.{HasRegMap, RegField} @@ -194,6 +194,8 @@ class GCDAXI4(params: GCDParams, beatBytes: Int)(implicit p: Parameters) extends trait CanHavePeripheryGCD { this: BaseSubsystem => private val portName = "gcd" + private val pbus = locateTLBusWrapper(PBUS) + // Only build if we are using the TL (nonAXI4) version val gcd_busy = p(GCDKey) match { case Some(params) => { diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala index 78237eca..6bf72343 100644 --- a/generators/chipyard/src/main/scala/example/InitZero.scala +++ b/generators/chipyard/src/main/scala/example/InitZero.scala @@ -2,7 +2,7 @@ package chipyard.example import chisel3._ import chisel3.util._ -import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes} +import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes, FBUS} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange} import freechips.rocketchip.tilelink._ @@ -62,6 +62,7 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem => p(InitZeroKey) .map { k => val initZero = LazyModule(new InitZero()(p)) + val fbus = locateTLBusWrapper(FBUS) fbus.coupleFrom("init-zero") { _ := initZero.node } } } diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index df2ec35a..cefd1915 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -199,6 +199,7 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p trait CanHavePeripheryStreamingFIR extends BaseSubsystem { val streamingFIR = p(GenericFIRKey) match { case Some(params) => { + val pbus = locateTLBusWrapper(PBUS) val domain = pbus.generateSynchronousDomain.suggestName("fir_domain") val streamingFIR = domain { LazyModule(new TLGenericFIRChain( genIn = FixedPoint(8.W, 3.BP), diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index a2259ab1..154a3650 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -131,6 +131,7 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => val passthrough = p(StreamingPassthroughKey) match { case Some(params) => { + val pbus = locateTLBusWrapper(PBUS) val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain") val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) } pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ } diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 80723b61..b4f116d2 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -5,7 +5,12 @@ import chisel3.reflect.DataMirror import chisel3.experimental.Analog import org.chipsalliance.cde.config._ -import freechips.rocketchip.diplomacy._ +import org.chipsalliance.diplomacy._ +import org.chipsalliance.diplomacy.nodes._ +import org.chipsalliance.diplomacy.aop._ +import org.chipsalliance.diplomacy.lazymodule._ +import org.chipsalliance.diplomacy.bundlebridge._ +import freechips.rocketchip.diplomacy.{Resource, ResourceBinding, ResourceAddress} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem._ @@ -165,11 +170,12 @@ case object IOCellKey extends Field[IOCellTypeParams](GenericIOCellParams()) class WithGPIOCells extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp) => { + (system: HasPeripheryGPIO) => { val (ports2d, cells2d) = system.gpio.zipWithIndex.map({ case (gpio, i) => gpio.pins.zipWithIndex.map({ case (pin, j) => + val p = system.asInstanceOf[BaseSubsystem].p val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}") - val iocell = system.p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}") + val iocell = p(IOCellKey).gpio().suggestName(s"iocell_gpio_${i}_${j}") iocell.io.o := pin.o.oval iocell.io.oe := pin.o.oe iocell.io.ie := pin.o.ie @@ -184,7 +190,7 @@ class WithGPIOCells extends OverrideIOBinder({ }) class WithGPIOPunchthrough extends OverrideIOBinder({ - (system: HasPeripheryGPIOModuleImp) => { + (system: HasPeripheryGPIO) => { val ports = system.gpio.zipWithIndex.map { case (gpio, i) => val io_gpio = IO(gpio.cloneType).suggestName(s"gpio_$i") io_gpio <> gpio @@ -195,7 +201,7 @@ class WithGPIOPunchthrough extends OverrideIOBinder({ }) class WithI2CPunchthrough extends OverrideIOBinder({ - (system: HasPeripheryI2CModuleImp) => { + (system: HasPeripheryI2C) => { val ports = system.i2c.zipWithIndex.map { case (i2c, i) => val io_i2c = IO(i2c.cloneType).suggestName(s"i2c_$i") io_i2c <> i2c @@ -207,11 +213,12 @@ class WithI2CPunchthrough extends OverrideIOBinder({ // DOC include start: WithUARTIOCells class WithUARTIOCells extends OverrideIOBinder({ - (system: HasPeripheryUARTModuleImp) => { + (system: HasPeripheryUART) => { val (ports: Seq[UARTPort], cells2d) = system.uart.zipWithIndex.map({ case (u, i) => - val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey), abstractResetAsAsync = true) + val p = system.asInstanceOf[BaseSubsystem].p + val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", p(IOCellKey), abstractResetAsAsync = true) val where = PBUS // TODO fix - val bus = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where) + val bus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(where) val freqMHz = bus.dtsFrequency.get / 1000000 (UARTPort(() => port, i, freqMHz.toInt), ios) }).unzip @@ -227,7 +234,7 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({ Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) } InModuleBody { - val spi = system.asInstanceOf[BaseSubsystem].module.asInstanceOf[HasPeripherySPIBundle].spi + val spi = system.spi val ports = spi.zipWithIndex.map({ case (s, i) => val io_spi = IO(s.cloneType).suggestName(s"spi_$i") io_spi <> s @@ -239,20 +246,20 @@ class WithSPIIOPunchthrough extends OverrideLazyIOBinder({ }) class WithSPIFlashIOCells extends OverrideIOBinder({ - (system: HasPeripherySPIFlashModuleImp) => { + (system: HasPeripherySPIFlash) => { val (ports: Seq[SPIFlashPort], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) => - + val p = system.asInstanceOf[BaseSubsystem].p val name = s"spi_${i}" val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name) val iocellBase = s"iocell_${name}" // SCK and CS are unidirectional outputs - val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey), IOCell.toAsyncReset) - val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), system.p(IOCellKey), IOCell.toAsyncReset) + val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), p(IOCellKey), IOCell.toAsyncReset) + val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs"), p(IOCellKey), IOCell.toAsyncReset) // DQ are bidirectional, so then need special treatment val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) => - val iocell = system.p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}") + val iocell = p(IOCellKey).gpio().suggestName(s"${iocellBase}_dq_${j}") iocell.io.o := pin.o iocell.io.oe := pin.oe iocell.io.ie := true.B @@ -261,7 +268,7 @@ class WithSPIFlashIOCells extends OverrideIOBinder({ iocell } - (SPIFlashPort(() => port, system.p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs) + (SPIFlashPort(() => port, p(PeripherySPIFlashKey)(i), i), dqIOs ++ csIOs ++ sckIOs) }).unzip (ports, cells2d.flatten) } @@ -419,7 +426,8 @@ class WithL2FBusAXI4Punchthrough extends OverrideLazyIOBinder({ (system: CanHaveSlaveAXI4Port) => { implicit val p: Parameters = GetSystemParameters(system) val clockSinkNode = p(ExtIn).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) - clockSinkNode.map(_ := system.asInstanceOf[BaseSubsystem].fbus.fixedClockNode) + val fbus = system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(FBUS) + clockSinkNode.map(_ := fbus.fixedClockNode) def clockBundle = clockSinkNode.get.in.head._1 InModuleBody { diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala index 6b327a18..a9ea0a2d 100644 --- a/generators/chipyard/src/main/scala/iobinders/Ports.scala +++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala @@ -16,8 +16,8 @@ import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4EdgeParameters} import freechips.rocketchip.subsystem.{MemoryPortParams, MasterPortParams, SlavePortParams} import freechips.rocketchip.devices.debug.{ClockedDMIIO} -import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.tilelink.{TLBundle} +import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag} trait Port[T <: Data] { val getIO: () => T diff --git a/generators/diplomacy b/generators/diplomacy new file mode 160000 index 00000000..e5a98245 --- /dev/null +++ b/generators/diplomacy @@ -0,0 +1 @@ +Subproject commit e5a98245d6d445e4fa156cb6cad987b1d6c99244 diff --git a/generators/fft-generator b/generators/fft-generator index 4e7e6cbb..490b975d 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit 4e7e6cbbbc6ed96d27dbaeb2413764cd446c50b3 +Subproject commit 490b975d36f49632f05c29dd22bcd6e5f0e703ab diff --git a/generators/nvdla b/generators/nvdla index 95697452..cfcb5faf 160000 --- a/generators/nvdla +++ b/generators/nvdla @@ -1 +1 @@ -Subproject commit 95697452e51ad56230a6e631bb02b3351c4293c6 +Subproject commit cfcb5fafcbf07035234a319622a0c4fa47ddef54 diff --git a/generators/rocc-acc-utils b/generators/rocc-acc-utils index b001c888..9b8c5d37 160000 --- a/generators/rocc-acc-utils +++ b/generators/rocc-acc-utils @@ -1 +1 @@ -Subproject commit b001c888f9620189cd13d2c6ba19f1e28663a3cb +Subproject commit 9b8c5d375fb89a3f4ff017e3b8933b63116382f6 diff --git a/generators/rocket-chip b/generators/rocket-chip index 8026b6bc..b3476b17 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 8026b6bc9abe7cbfb7d07cecb28ef909c25868c8 +Subproject commit b3476b17df69401b4f8a5bcc400f0ab3259aa631 diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks index f9263535..2e98a5ea 160000 --- a/generators/rocket-chip-blocks +++ b/generators/rocket-chip-blocks @@ -1 +1 @@ -Subproject commit f9263535be1988778f1baf98c18221dee1db1a47 +Subproject commit 2e98a5eafbc978d4aef3a0e463f3a2c94145ee50 diff --git a/generators/testchipip b/generators/testchipip index 5d6ec23c..104df6a8 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 5d6ec23cd6d60299615700c00021fc5f69f57788 +Subproject commit 104df6a81fd989cd4cad69b699894664fcf93c05 diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index 39d9d75f..b1062cda 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -23,7 +23,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem case t: boom.v4.lsu.BoomTraceGenTile => t.statusNode.makeSink() } - lazy val fakeClockDomain = sbus.generateSynchronousDomain + lazy val fakeClockDomain = locateTLBusWrapper("sbus").generateSynchronousDomain lazy val clintOpt = None lazy val debugOpt = None diff --git a/sims/firesim b/sims/firesim index cc6cb810..f1646fba 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit cc6cb810e53267acdc567ee5c13e3e01c0e12dd9 +Subproject commit f1646fbae2423aa13a1ab3dea8fd54d5389e50b3 diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils index 272cee3c..24bf9a27 160000 --- a/tools/rocket-dsp-utils +++ b/tools/rocket-dsp-utils @@ -1 +1 @@ -Subproject commit 272cee3c83a31a7496b8f2e933290798e2fb5cac +Subproject commit 24bf9a27a8fe565392f1a6aa3e53fdbe92a64dbc