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Fix Arty merge and errors from CY bump

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This commit is contained in:
abejgonzalez
2020-11-05 15:04:44 -08:00
parent a7ab0dab59
commit a281869041
6 changed files with 89 additions and 106 deletions
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2
fpga/Makefile
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@@ -48,7 +48,7 @@ ifeq ($(SUB_PROJECT),arty)
MODEL ?= ArtyFPGATestHarness
VLOG_MODEL ?= ArtyFPGATestHarness
MODEL_PACKAGE ?= chipyard.fpga.arty
CONFIG ?= E300ArtyDevKitConfig
CONFIG ?= TinyRocketArtyConfig
CONFIG_PACKAGE ?= chipyard.fpga.arty
GENERATOR_PACKAGE ?= chipyard
TB ?= none # unused

39
fpga/src/main/scala/arty/Configs.scala
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@@ -9,35 +9,13 @@ import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
import freechips.rocketchip.system._
import freechips.rocketchip.tile._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.pwm._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._
import chipyard.{BuildSystem}
import chipyard.iobinders
class E300DevKitExtra extends Config((site, here, up) => {
case PeripheryGPIOKey => List(
GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
case PeripheryPWMKey => List(
PWMParams(address = 0x10015000, cmpWidth = 8),
PWMParams(address = 0x10025000, cmpWidth = 16),
PWMParams(address = 0x10035000, cmpWidth = 16))
case PeripherySPIKey => List(
SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3),
SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3))
case PeripherySPIFlashKey => List(
SPIFlashParams(
fAddress = 0x20000000,
rAddress = 0x10014000,
defaultSampleDel = 3))
class WithDefaultPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(
UARTParams(address = 0x10013000),
UARTParams(address = 0x10023000))
case PeripheryI2CKey => List(
I2CParams(address = 0x10016000))
UARTParams(address = 0x10013000))
case DTSTimebase => BigInt(32768)
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2,
@@ -46,17 +24,16 @@ class E300DevKitExtra extends Config((site, here, up) => {
debugIdleCycles = 5)
})
class WithE300System extends Config((site, here, up) => {
case BuildSystem => (p: Parameters) => new E300DigitalTop()(p)
})
class E300ArtyDevKitConfig extends Config(
new WithE300System ++
class TinyRocketArtyConfig extends Config(
new WithArtyJTAGHarnessBinder ++
new WithArtyUARTHarnessBinder ++
new WithArtyResetHarnessBinder ++
new chipyard.iobinders.WithDebugIOCells ++
new chipyard.iobinders.WithUARTIOCells ++
new E300DevKitExtra ++
new WithResetPassthrough ++
new WithDefaultPeripherals ++
new chipyard.config.WithNoSubsystemDrivenClocks ++
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.With1TinyCore ++

21
fpga/src/main/scala/arty/DigitalTop.scala
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@@ -1,21 +0,0 @@
package chipyard.fpga.arty
import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.tilelink._
import chipyard.{DigitalTop, DigitalTopModule}
// ------------------------------------
// E300 DigitalTop
// ------------------------------------
class E300DigitalTop(implicit p: Parameters) extends DigitalTop
{
override lazy val module = new E300DigitalTopModule(this)
}
class E300DigitalTopModule[+L <: E300DigitalTop](l: L) extends DigitalTopModule(l)

90
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -1,71 +1,69 @@
package chipyard.fpga.arty
import chisel3._
import chisel3.experimental.{Analog}
import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.subsystem._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._
import barstools.iocell.chisel._
import testchipip._
import chipyard.harness.OverrideHarnessBinder
import chipyard.HasHarnessSignalReferences
import chipyard.iobinders.GetSystemParameters
import tracegen.{TraceGenSystemModuleImp}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import scala.reflect.{ClassTag}
import sifive.blocks.devices.jtag._
import sifive.blocks.devices.pinctrl._
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
class WithArtyJTAGHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[JTAGIO]) => {
// (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
// ports.map {
// case d: ClockedDMIIO =>
// // Want to error here.
// case j: JTAGIO =>
// //val dtm_success = WireInit(false.B)
// //when (dtm_success) { th.success := true.B }
// //val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success)
import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
// j.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asUInt
class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
(system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) {
// Debug module reset
th.dut_ndreset := ports(0)
// IOBUF(th.jd_5, j.TMS)
// PULLUP(th.jd_5)
// JTAG reset
ports(1) := PowerOnResetFPGAOnly(th.clock_32MHz)
}
}
})
// IOBUF(th.jd_4, j.TDI)
// PULLUP(th.jd_4)
class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
ports.map {
case j: JTAGIO =>
withClockAndReset(th.harnessClock, th.hReset) {
val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
// IOBUF(th.jd_0, j.TDO)
JTAGPinsFromPort(io_jtag, j)
// // mimic putting a pullup on this line (part of reset vote)
// th.SRST_n := IOBUF(th.jd_6)
// PULLUP(th.jd_6)
io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool
// IOBUF(th.jd_1, j.TRSTn)
// PULLUP(th.jd_1)
// }
IOBUF(th.jd_5, io_jtag.TMS)
PULLUP(th.jd_5)
IOBUF(th.jd_4, io_jtag.TDI)
PULLUP(th.jd_4)
IOBUF(th.jd_0, io_jtag.TDO)
// mimic putting a pullup on this line (part of reset vote)
th.SRST_n := IOBUF(th.jd_6)
PULLUP(th.jd_6)
// ignore the po input
io_jtag.TCK.i.po.map(_ := DontCare)
io_jtag.TDI.i.po.map(_ := DontCare)
io_jtag.TMS.i.po.map(_ := DontCare)
io_jtag.TDO.i.po.map(_ := DontCare)
}
}
}
})
class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
(system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
// (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
// UARTAdapter.connect(ports)(system.p)
// IOBUF(th.ck_io(2), ports.txd)
// IOBUF(th.ck_io(3), ports.rxd)
withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_txd_in, ports.head.txd)
ports.head.rxd := IOBUF(th.uart_rxd_out)
}
}
})

24
fpga/src/main/scala/arty/IOBinders.scala Normal file
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@@ -0,0 +1,24 @@
package chipyard.fpga.arty
import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.util._
import freechips.rocketchip.devices.debug._
import chipyard.iobinders.{ComposeIOBinder}
class WithResetPassthrough extends ComposeIOBinder({
(system: HasPeripheryDebugModuleImp) => {
// Debug module reset
val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset")
io_ndreset := system.debug.get.ndreset
// JTAG reset
val sjtag = system.debug.get.systemjtag.get
val io_sjtag_reset: Bool = IO(Input(Bool())).suggestName("sjtag_reset")
sjtag.reset := io_sjtag_reset
(Seq(io_ndreset, io_sjtag_reset), Nil)
}
})

19
fpga/src/main/scala/arty/TestHarness.scala
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@@ -1,23 +1,27 @@
package chipyard.fpga.arty
import chisel3._
import chisel3.experimental.{Analog}
import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.config.{Parameters}
import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions}
import chipyard.harness.{ApplyHarnessBinders}
import chipyard.iobinders.{HasIOBinders}
import chipyard.harness.{ApplyHarnessBinders, HarnessBinders}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessSignalReferences {
val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
// turn IO clock into Reset type
// Convert harness resets from Bool to Reset type.
val hReset = Wire(Reset())
hReset := ck_rst
val dReset = Wire(AsyncReset())
dReset := reset_core.asAsyncReset
// default to 32MHz clock
withClockAndReset(clock_32MHz, hReset) {
val dut = Module(lazyDut.module)
@@ -27,13 +31,14 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
val harnessReset = hReset
val success = false.B
val dutReset = reset_core
val dutReset = dReset
// must be after HasHarnessSignalReferences assignments
lazyDut match { case d: HasTestHarnessFunctions =>
d.harnessFunctions.foreach(_(this))
}
lazyDut match { case d: HasIOBinders =>
ApplyHarnessBinders(this, d.lazySystem, d.portMap)
}
}