[skip ci] update some docs, merge VLSI_RTL and VLSI_BB into one

docs/VLSI/ASAP7-Tutorial.rst

@@ -20,7 +20,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
 * ``env.yml``
 
-  * A template file for tool environment configuration. Fill in the install and license server paths for your environment.
+  * A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
 
 * ``example-vlsi``
 
@@ -28,7 +28,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
 * ``example-asap7.yml``, ``example-tools.yml``
 
-  * Hammer IR for this tutorial.
+  * Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
 
 * ``example-design.yml``, ``example-sky130.yml``, ``example-tech.yml``
 
@@ -38,9 +38,9 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
   * All of the elaborated Chisel and FIRRTL.
 
-* ``hammer``, ``hammer-<vendor>-plugins``, ``hammer-<tech>-plugin``
+* ``hammer-<vendor>-plugins``
 
-  * Core, tool, tech repositories.
+  * Tool plugin repositories.
 
 * ``view_gds.py``
 

docs/VLSI/Sky130-Commercial-Tutorial.rst

@@ -20,7 +20,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
 * ``env.yml``
 
-  * A template file for tool environment configuration. Fill in the install and license server paths for your environment.
+  * A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
 
 * ``example-vlsi-sky130``
 
@@ -28,7 +28,7 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
 * ``example-sky130.yml``, ``example-tools.yml``, ``example-designs/sky130-commercial.yml``
 
-  * Hammer IR for this tutorial.
+  * Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
 
 * ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml``
 
@@ -38,9 +38,9 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
   * All of the elaborated Chisel and FIRRTL.
 
-* ``hammer``, ``hammer-<vendor>-plugins``, ``hammer-<tech>-plugin``
+* ``hammer-<vendor>-plugins``
 
-  * Core, tool, tech repositories.
+  * Tool plugin repositories.
 
 Prerequisites
 -------------

docs/VLSI/Sky130-OpenROAD-Tutorial.rst

@@ -18,13 +18,17 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
   * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable.
   * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files.
 
+* ``env.yml``
+
+  * A template file for tool environment configuration. Fill in the install and license server paths for your environment. For SLICE and BWRC affiliates, example environment configs are found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/env>`__.
+
 * ``example-vlsi-sky130``
 
   * Entry point to Hammer. Contains example placeholders for hooks.
 
 * ``example-sky130.yml``, ``example-openroad.yml``, ``example-designs/sky130-openroad.yml``
 
-  * Hammer IR for this tutorial.
+  * Hammer IR for this tutorial. For SLICE and BWRC affiliates, an example ASAP7 config is found `here <https://github.com/ucb-bar/hammer/tree/master/e2e/pdks>`__.
 
 * ``example-design.yml``, ``example-asap7.yml``, ``example-tech.yml``
 
@@ -34,9 +38,9 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
   * All of the elaborated Chisel and FIRRTL.
 
-* ``hammer``, ``hammer/src/hammer-vlsi/<syn-par-drc-lvs>/<tool>``, ``hammer/src/hammer-vlsi/technology/<tech>``
+* ``hammer-<vendor>-plugins``
 
-  * Core repository, and open-source tool and technology plugins.
+  * Tool plugin repositories not used for this tutorial (they are provided in the hammer-vlsi package).
 
 Prerequisites
 -------------

vlsi/Makefile

@@ -57,11 +57,14 @@ endif
 #########################################################################################
 ifneq ($(CUSTOM_VLOG), )
 	VLSI_RTL = $(CUSTOM_VLOG)
-	VLSI_BB =
 else
-	VLSI_RTL = $(shell cat $(TOP_MODS_FILELIST)) $(TOP_SMEMS_FILE) 
-	# TODO: have MFC split top & harness blackboxes
-	VLSI_BB = $(build_dir)/EICG_wrapper.v $(TOP_BB_MODS_FILELIST)
+	# This one-liner does a few things. Line-by-line:
+	# 1. concatenates the .top.f and .bb.f files and uniquifies them
+	# 2. removes all harness blackboxes with DPI calls (SimJTAG, etc.)
+	# 3. append EICG_wrapper.v and the compiled memories
+	VLSI_RTL = $(shell cat $(TOP_MODS_FILELIST) $(BB_MODS_FILELIST) | sort | uniq | \
+			   rev | sed -E 's/cc(.*)/c\1/g' | uniq -s 1 | sed '/c\./d' | rev) \
+			   $(build_dir)/EICG_wrapper.v $(TOP_SMEMS_FILE)
 endif
 
 .PHONY: default
@@ -222,12 +225,12 @@ ifeq ($(CUSTOM_VLOG), )
 	GENERATED_CONFS += $(SRAM_CONF)
 endif
 
-$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
+$(SYN_CONF): $(VLSI_RTL)
 	mkdir -p $(dir $@)
 	echo "synthesis.inputs:" >> $@
 	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  input_files:" >> $@
-	for x in $(VLSI_RTL) $(VLSI_BB); do \
+	for x in $(VLSI_RTL); do \
 		echo '    - "'$$x'"' >> $@; \
 	done