First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.
This commit is contained in:
James Dunn
23
fpga/Makefile.e300artydevkit
Normal file
23
fpga/Makefile.e300artydevkit
Normal file
@@ -0,0 +1,23 @@
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# See LICENSE for license details.
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base_dir=$(abspath ..)
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BUILD_DIR := $(base_dir)/fpga/builds/e300artydevkit
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FPGA_DIR := $(base_dir)/fpga/fpga-shells/xilinx
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MODEL := E300ArtyDevKitFPGAChip
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PROJECT := sifive.freedom.everywhere.e300artydevkit
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export CONFIG_PROJECT := sifive.freedom.everywhere.e300artydevkit
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export CONFIG := E300ArtyDevKitConfig
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export BOARD := arty
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export BOOTROM_DIR := $(base_dir)/fpga/bootrom/xip
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rocketchip_dir := $(base_dir)/generators/rocket-chip
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sifiveblocks_dir := $(base_dir)/generators/sifive-blocks
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VSRCS := \
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$(rocketchip_dir)/src/main/resources/vsrc/AsyncResetReg.v \
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$(rocketchip_dir)/src/main/resources/vsrc/plusarg_reader.v \
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$(rocketchip_dir)/src/main/resources/vsrc/EICG_wrapper.v \
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$(sifiveblocks_dir)/vsrc/SRLatch.v \
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$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
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$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
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$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
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include common.mk
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45
fpga/bootrom/xip/Makefile
Normal file
45
fpga/bootrom/xip/Makefile
Normal file
@@ -0,0 +1,45 @@
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# RISCV environment variable must be set
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CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
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OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
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CFLAGS=-march=rv32imac -mabi=ilp32 -O2 -std=gnu11 -Wall -I. -nostartfiles -fno-common -g
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LFLAGS=-static -nostdlib
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dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb
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$(dtb): $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts
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dtc -I dts -O dtb -o $@ $<
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.PHONY: dtb
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dtb: $(dtb)
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elf := $(BUILD_DIR)/xip.elf
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$(elf): xip.S $(dtb)
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$(CC) $(CFLAGS) -DXIP_TARGET_ADDR=0x20400000 -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o $@ $<
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.PHONY: elf
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elf: $(elf)
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bin := $(BUILD_DIR)/xip.bin
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$(bin): $(elf)
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$(OBJCOPY) -O binary $< $@
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.PHONY: bin
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bin: $(bin)
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hex := $(BUILD_DIR)/xip.hex
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$(hex): $(bin)
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od -t x4 -An -w4 -v $< > $@
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.PHONY: hex
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hex: $(hex)
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romgen := $(BUILD_DIR)/rom.v
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$(romgen): $(hex)
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$(rocketchip_dir)/scripts/vlsi_rom_gen $(ROMCONF) $< > $@
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.PHONY: romgen
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romgen: $(romgen)
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.PHONY: clean
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clean::
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rm -rf $(hex) $(elf)
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16
fpga/bootrom/xip/xip.S
Normal file
16
fpga/bootrom/xip/xip.S
Normal file
@@ -0,0 +1,16 @@
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// See LICENSE for license details.
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// Execute in place
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// Jump directly to XIP_TARGET_ADDR
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.section .text.init
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.option norvc
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.globl _start
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_start:
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csrr a0, mhartid
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la a1, dtb
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li t0, XIP_TARGET_ADDR
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jr t0
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.section .rodata
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dtb:
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.incbin DEVICE_TREE
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119
fpga/common.mk
Normal file
119
fpga/common.mk
Normal file
@@ -0,0 +1,119 @@
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# See LICENSE for license details.
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# Required variables:
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# - MODEL
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# - PROJECT
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# - CONFIG_PROJECT
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# - CONFIG
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# - BUILD_DIR
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# - FPGA_DIR
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# Optional variables:
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# - EXTRA_FPGA_VSRCS
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# export to bootloader
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export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf
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# export to fpga-shells
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export FPGA_TOP_SYSTEM=$(MODEL)
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export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM)
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export fpga_common_script_dir=$(FPGA_DIR)/common/tcl
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export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl
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export BUILD_DIR
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EXTRA_FPGA_VSRCS ?=
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PATCHVERILOG ?= ""
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BOOTROM_DIR ?= ""
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base_dir=$(abspath ..)
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export rocketchip_dir := $(base_dir)/generators/rocket-chip
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SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar ++2.12.10
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SBT_PROJECT ?= chipyard
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firrtl_dir := $(base_dir)/tools/firrtl
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# Build firrtl.jar and put it where chisel3 can find it.
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FIRRTL_JAR := $(base_dir)/lib/firrtl.jar
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FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Driver
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$(FIRRTL_JAR): $(shell find $(firrtl_dir)/src/main/scala -iname "*.scala")
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$(MAKE) -C $(firrtl_dir) SBT="$(SBT)" root_dir=$(firrtl_dir) build-scala
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mkdir -p $(base_dir)/lib
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cp $(firrtl_dir)/utils/bin/firrtl.jar $(FIRRTL_JAR)
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# Build .fir
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long_name := $(CONFIG_PROJECT).$(CONFIG)
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firrtl := $(BUILD_DIR)/$(long_name).fir
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$(firrtl): $(shell find $(base_dir) -name '*.scala') $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "project freedomPlatforms" \
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"runMain chipyard.Generator \
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--target-dir $(BUILD_DIR) \
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--name $(long_name) \
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--top-module $(PROJECT).$(MODEL) \
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--legacy-configs $(CONFIG_PROJECT).$(CONFIG)"
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.PHONY: firrtl
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firrtl: $(firrtl)
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# Build .v
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verilog := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
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$(verilog): $(firrtl) $(FIRRTL_JAR)
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$(FIRRTL) -i $(firrtl) -o $@ -X verilog
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ifneq ($(PATCHVERILOG),"")
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$(PATCHVERILOG)
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endif
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.PHONY: verilog
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verilog: $(verilog)
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romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
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$(romgen): $(verilog)
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ifneq ($(BOOTROM_DIR),"")
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$(MAKE) -C $(BOOTROM_DIR) romgen
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mv $(BUILD_DIR)/rom.v $@
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endif
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.PHONY: romgen
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romgen: $(romgen)
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f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F
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$(f):
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echo $(VSRCS) > $@
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bit := $(BUILD_DIR)/obj/$(MODEL).bit
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$(bit): $(romgen) $(f)
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cd $(BUILD_DIR); vivado \
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-nojournal -mode batch \
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-source $(fpga_common_script_dir)/vivado.tcl \
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-tclargs \
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-top-module "$(MODEL)" \
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-F "$(f)" \
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-ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
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-board "$(BOARD)"
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# Build .mcs
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mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
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$(mcs): $(bit)
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cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
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.PHONY: mcs
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mcs: $(mcs)
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# Build Libero project
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prjx := $(BUILD_DIR)/libero/$(MODEL).prjx
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$(prjx): $(verilog)
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cd $(BUILD_DIR); libero SCRIPT:$(fpga_common_script_dir)/libero.tcl SCRIPT_ARGS:"$(BUILD_DIR) $(MODEL) $(PROJECT) $(CONFIG) $(BOARD)"
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.PHONY: prjx
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prjx: $(prjx)
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# Clean
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.PHONY: clean
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clean:
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ifneq ($(BOOTROM_DIR),"")
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$(MAKE) -C $(BOOTROM_DIR) clean
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endif
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$(MAKE) -C $(FPGA_DIR) clean
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rm -rf $(BUILD_DIR)
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1
fpga/fpga-shells
Submodule
1
fpga/fpga-shells
Submodule
Submodule fpga/fpga-shells added at e8e7f8a321
65
fpga/src/main/scala/arty/Config.scala
Normal file
65
fpga/src/main/scala/arty/Config.scala
Normal file
@@ -0,0 +1,65 @@
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// See LICENSE for license details.
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package sifive.freedom.everywhere.e300artydevkit
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
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import freechips.rocketchip.system._
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import freechips.rocketchip.tile._
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import sifive.blocks.devices.mockaon._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.pwm._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.i2c._
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// Default FreedomEConfig
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class DefaultFreedomEConfig extends Config (
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new WithNBreakpoints(2) ++
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new WithNExtTopInterrupts(0) ++
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new WithJtagDTM ++
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new TinyConfig
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)
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// Freedom E300 Arty Dev Kit Peripherals
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class E300DevKitPeripherals extends Config((site, here, up) => {
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case PeripheryGPIOKey => List(
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GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
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case PeripheryPWMKey => List(
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PWMParams(address = 0x10015000, cmpWidth = 8),
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PWMParams(address = 0x10025000, cmpWidth = 16),
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PWMParams(address = 0x10035000, cmpWidth = 16))
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case PeripherySPIKey => List(
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SPIParams(csWidth = 4, rAddress = 0x10024000, defaultSampleDel = 3),
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SPIParams(csWidth = 1, rAddress = 0x10034000, defaultSampleDel = 3))
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case PeripherySPIFlashKey => List(
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SPIFlashParams(
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fAddress = 0x20000000,
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rAddress = 0x10014000,
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defaultSampleDel = 3))
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case PeripheryUARTKey => List(
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UARTParams(address = 0x10013000),
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UARTParams(address = 0x10023000))
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case PeripheryI2CKey => List(
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I2CParams(address = 0x10016000))
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case PeripheryMockAONKey =>
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MockAONParams(address = 0x10000000)
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case PeripheryMaskROMKey => List(
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MaskROMParams(address = 0x10000, name = "BootROM"))
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})
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// Freedom E300 Arty Dev Kit Peripherals
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class E300ArtyDevKitConfig extends Config(
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new E300DevKitPeripherals ++
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new DefaultFreedomEConfig().alter((site,here,up) => {
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case DTSTimebase => BigInt(32768)
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case JtagDTMKey => new JtagDTMConfig (
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idcodeVersion = 2,
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idcodePartNum = 0x000,
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idcodeManufId = 0x489,
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debugIdleCycles = 5)
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})
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)
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193
fpga/src/main/scala/arty/FPGAChip.scala
Normal file
193
fpga/src/main/scala/arty/FPGAChip.scala
Normal file
@@ -0,0 +1,193 @@
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// See LICENSE for license details.
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package sifive.freedom.everywhere.e300artydevkit
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import Chisel._
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import chisel3.core.{attach}
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import chisel3.experimental.{withClockAndReset}
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy.{LazyModule}
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.spi._
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import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
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import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
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//-------------------------------------------------------------------------
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// E300ArtyDevKitFPGAChip
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//-------------------------------------------------------------------------
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class E300ArtyDevKitFPGAChip(implicit override val p: Parameters) extends ArtyShell {
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//-----------------------------------------------------------------------
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// Clock divider
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//-----------------------------------------------------------------------
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val slow_clock = Wire(Bool())
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// Divide clock by 256, used to generate 32.768 kHz clock for AON block
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withClockAndReset(clock_8MHz, ~mmcm_locked) {
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val clockToggleReg = RegInit(false.B)
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val (_, slowTick) = Counter(true.B, 256)
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when (slowTick) {clockToggleReg := ~clockToggleReg}
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slow_clock := clockToggleReg
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}
|
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//-----------------------------------------------------------------------
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// DUT
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//-----------------------------------------------------------------------
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withClockAndReset(clock_32MHz, ck_rst) {
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val dut = Module(new E300ArtyDevKitPlatform)
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//---------------------------------------------------------------------
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// SPI flash IOBUFs
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//---------------------------------------------------------------------
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IOBUF(qspi_sck, dut.io.pins.qspi.sck)
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IOBUF(qspi_cs, dut.io.pins.qspi.cs(0))
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IOBUF(qspi_dq(0), dut.io.pins.qspi.dq(0))
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IOBUF(qspi_dq(1), dut.io.pins.qspi.dq(1))
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IOBUF(qspi_dq(2), dut.io.pins.qspi.dq(2))
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IOBUF(qspi_dq(3), dut.io.pins.qspi.dq(3))
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//---------------------------------------------------------------------
|
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// JTAG IOBUFs
|
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//---------------------------------------------------------------------
|
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dut.io.pins.jtag.TCK.i.ival := IBUFG(IOBUF(jd_2).asClock).asUInt
|
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IOBUF(jd_5, dut.io.pins.jtag.TMS)
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PULLUP(jd_5)
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IOBUF(jd_4, dut.io.pins.jtag.TDI)
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PULLUP(jd_4)
|
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IOBUF(jd_0, dut.io.pins.jtag.TDO)
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|
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// mimic putting a pullup on this line (part of reset vote)
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SRST_n := IOBUF(jd_6)
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PULLUP(jd_6)
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|
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// jtag reset
|
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val jtag_power_on_reset = PowerOnResetFPGAOnly(clock_32MHz)
|
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dut.io.jtag_reset := jtag_power_on_reset
|
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|
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// debug reset
|
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dut_ndreset := dut.io.ndreset
|
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|
||||
//---------------------------------------------------------------------
|
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// Assignment to package pins
|
||||
//---------------------------------------------------------------------
|
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// Pins IO0-IO13
|
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//
|
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// FTDI UART TX/RX are not connected to ck_io[0,1]
|
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// the way they are on Arduino boards. We copy outgoing
|
||||
// data to both places, switch 3 (sw[3]) determines whether
|
||||
// input to UART comes from FTDI chip or gpio_16 (shield pin PD0)
|
||||
|
||||
val iobuf_ck0 = Module(new IOBUF())
|
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iobuf_ck0.io.I := dut.io.pins.gpio.pins(16).o.oval
|
||||
iobuf_ck0.io.T := ~dut.io.pins.gpio.pins(16).o.oe
|
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attach(iobuf_ck0.io.IO, ck_io(0)) // UART0 RX
|
||||
|
||||
val iobuf_uart_txd = Module(new IOBUF())
|
||||
iobuf_uart_txd.io.I := dut.io.pins.gpio.pins(16).o.oval
|
||||
iobuf_uart_txd.io.T := ~dut.io.pins.gpio.pins(16).o.oe
|
||||
attach(iobuf_uart_txd.io.IO, uart_txd_in)
|
||||
|
||||
// gpio(16) input is shared between FTDI TX pin and the Arduino shield pin using SW[3]
|
||||
val sw_3_in = IOBUF(sw_3)
|
||||
dut.io.pins.gpio.pins(16).i.ival := Mux(sw_3_in,
|
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iobuf_ck0.io.O & dut.io.pins.gpio.pins(16).o.ie,
|
||||
iobuf_uart_txd.io.O & dut.io.pins.gpio.pins(16).o.ie)
|
||||
|
||||
IOBUF(uart_rxd_out, dut.io.pins.gpio.pins(17))
|
||||
|
||||
// Shield header row 0: PD2-PD7
|
||||
IOBUF(ck_io(2), dut.io.pins.gpio.pins(18))
|
||||
IOBUF(ck_io(3), dut.io.pins.gpio.pins(19)) // PWM1(1)
|
||||
IOBUF(ck_io(4), dut.io.pins.gpio.pins(20)) // PWM1(0)
|
||||
IOBUF(ck_io(5), dut.io.pins.gpio.pins(21)) // PWM1(2)
|
||||
IOBUF(ck_io(6), dut.io.pins.gpio.pins(22)) // PWM1(3)
|
||||
IOBUF(ck_io(7), dut.io.pins.gpio.pins(23))
|
||||
|
||||
// Header row 1: PB0-PB5
|
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IOBUF(ck_io(8), dut.io.pins.gpio.pins(0)) // PWM0(0)
|
||||
IOBUF(ck_io(9), dut.io.pins.gpio.pins(1)) // PWM0(1)
|
||||
IOBUF(ck_io(10), dut.io.pins.gpio.pins(2)) // SPI CS(0) / PWM0(2)
|
||||
IOBUF(ck_io(11), dut.io.pins.gpio.pins(3)) // SPI MOSI / PWM0(3)
|
||||
IOBUF(ck_io(12), dut.io.pins.gpio.pins(4)) // SPI MISO
|
||||
IOBUF(ck_io(13), dut.io.pins.gpio.pins(5)) // SPI SCK
|
||||
|
||||
dut.io.pins.gpio.pins(6).i.ival := 0.U
|
||||
dut.io.pins.gpio.pins(7).i.ival := 0.U
|
||||
dut.io.pins.gpio.pins(8).i.ival := 0.U
|
||||
|
||||
// Header row 3: A0-A5 (we don't support using them as analog inputs)
|
||||
// just treat them as regular digital GPIOs
|
||||
IOBUF(ck_io(15), dut.io.pins.gpio.pins(9)) // A1 = CS(2)
|
||||
IOBUF(ck_io(16), dut.io.pins.gpio.pins(10)) // A2 = CS(3) / PWM2(0)
|
||||
IOBUF(ck_io(17), dut.io.pins.gpio.pins(11)) // A3 = PWM2(1)
|
||||
IOBUF(ck_io(18), dut.io.pins.gpio.pins(12)) // A4 = PWM2(2) / SDA
|
||||
IOBUF(ck_io(19), dut.io.pins.gpio.pins(13)) // A5 = PWM2(3) / SCL
|
||||
|
||||
// Mirror outputs of GPIOs with PWM peripherals to RGB LEDs on Arty
|
||||
// assign RGB LED0 R,G,B inputs = PWM0(1,2,3) when iof_1 is active
|
||||
IOBUF(led0_r, dut.io.pins.gpio.pins(1))
|
||||
IOBUF(led0_g, dut.io.pins.gpio.pins(2))
|
||||
IOBUF(led0_b, dut.io.pins.gpio.pins(3))
|
||||
|
||||
// Note that this is the one which is actually connected on the HiFive/Crazy88
|
||||
// Board. Same with RGB LED1 R,G,B inputs = PWM1(1,2,3) when iof_1 is active
|
||||
IOBUF(led1_r, dut.io.pins.gpio.pins(19))
|
||||
IOBUF(led1_g, dut.io.pins.gpio.pins(21))
|
||||
IOBUF(led1_b, dut.io.pins.gpio.pins(22))
|
||||
|
||||
// and RGB LED2 R,G,B inputs = PWM2(1,2,3) when iof_1 is active
|
||||
IOBUF(led2_r, dut.io.pins.gpio.pins(11))
|
||||
IOBUF(led2_g, dut.io.pins.gpio.pins(12))
|
||||
IOBUF(led2_b, dut.io.pins.gpio.pins(13))
|
||||
|
||||
// Only 19 out of 20 shield pins connected to GPIO pins
|
||||
// Shield pin A5 (pin 14) left unconnected
|
||||
// The buttons are connected to some extra GPIO pins not connected on the
|
||||
// HiFive1 board
|
||||
IOBUF(btn_0, dut.io.pins.gpio.pins(15))
|
||||
IOBUF(btn_1, dut.io.pins.gpio.pins(30))
|
||||
IOBUF(btn_2, dut.io.pins.gpio.pins(31))
|
||||
|
||||
val iobuf_btn_3 = Module(new IOBUF())
|
||||
iobuf_btn_3.io.I := ~dut.io.pins.aon.pmu.dwakeup_n.o.oval
|
||||
iobuf_btn_3.io.T := ~dut.io.pins.aon.pmu.dwakeup_n.o.oe
|
||||
attach(btn_3, iobuf_btn_3.io.IO)
|
||||
dut.io.pins.aon.pmu.dwakeup_n.i.ival := ~iobuf_btn_3.io.O & dut.io.pins.aon.pmu.dwakeup_n.o.ie
|
||||
|
||||
// UART1 RX/TX pins are assigned to PMOD_D connector pins 0/1
|
||||
IOBUF(ja_0, dut.io.pins.gpio.pins(25)) // UART1 TX
|
||||
IOBUF(ja_1, dut.io.pins.gpio.pins(24)) // UART1 RX
|
||||
|
||||
// SPI2 pins mapped to 6 pin ICSP connector (standard on later
|
||||
// arduinos) These are connected to some extra GPIO pins not connected
|
||||
// on the HiFive1 board
|
||||
IOBUF(ck_ss, dut.io.pins.gpio.pins(26))
|
||||
IOBUF(ck_mosi, dut.io.pins.gpio.pins(27))
|
||||
IOBUF(ck_miso, dut.io.pins.gpio.pins(28))
|
||||
IOBUF(ck_sck, dut.io.pins.gpio.pins(29))
|
||||
|
||||
// Use the LEDs for some more useful debugging things
|
||||
IOBUF(led_0, ck_rst)
|
||||
IOBUF(led_1, SRST_n)
|
||||
IOBUF(led_2, dut.io.pins.aon.pmu.dwakeup_n.i.ival)
|
||||
IOBUF(led_3, dut.io.pins.gpio.pins(14))
|
||||
|
||||
//---------------------------------------------------------------------
|
||||
// Unconnected inputs
|
||||
//---------------------------------------------------------------------
|
||||
|
||||
dut.io.pins.aon.erst_n.i.ival := ~reset_periph
|
||||
dut.io.pins.aon.lfextclk.i.ival := slow_clock
|
||||
dut.io.pins.aon.pmu.vddpaden.i.ival := 1.U
|
||||
}
|
||||
}
|
||||
178
fpga/src/main/scala/arty/Platform.scala
Normal file
178
fpga/src/main/scala/arty/Platform.scala
Normal file
@@ -0,0 +1,178 @@
|
||||
// See LICENSE for license details.
|
||||
package sifive.freedom.everywhere.e300artydevkit
|
||||
|
||||
import Chisel._
|
||||
|
||||
import freechips.rocketchip.config._
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.devices.debug._
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util.ResetCatchAndSync
|
||||
import freechips.rocketchip.system._
|
||||
|
||||
import sifive.blocks.devices.mockaon._
|
||||
import sifive.blocks.devices.gpio._
|
||||
import sifive.blocks.devices.jtag._
|
||||
import sifive.blocks.devices.pwm._
|
||||
import sifive.blocks.devices.spi._
|
||||
import sifive.blocks.devices.uart._
|
||||
import sifive.blocks.devices.i2c._
|
||||
import sifive.blocks.devices.pinctrl._
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// PinGen
|
||||
//-------------------------------------------------------------------------
|
||||
|
||||
object PinGen {
|
||||
def apply(): BasePin = {
|
||||
val pin = new BasePin()
|
||||
pin
|
||||
}
|
||||
}
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// E300ArtyDevKitPlatformIO
|
||||
//-------------------------------------------------------------------------
|
||||
|
||||
class E300ArtyDevKitPlatformIO(implicit val p: Parameters) extends Bundle {
|
||||
val pins = new Bundle {
|
||||
val jtag = new JTAGPins(() => PinGen(), false)
|
||||
val gpio = new GPIOPins(() => PinGen(), p(PeripheryGPIOKey)(0))
|
||||
val qspi = new SPIPins(() => PinGen(), p(PeripherySPIFlashKey)(0))
|
||||
val aon = new MockAONWrapperPins()
|
||||
}
|
||||
val jtag_reset = Bool(INPUT)
|
||||
val ndreset = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// E300ArtyDevKitPlatform
|
||||
//-------------------------------------------------------------------------
|
||||
|
||||
class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
|
||||
val sys = Module(LazyModule(new E300ArtyDevKitSystem).module)
|
||||
val io = new E300ArtyDevKitPlatformIO
|
||||
|
||||
// This needs to be de-asserted synchronously to the coreClk.
|
||||
val async_corerst = sys.aon.rsts.corerst
|
||||
// Add in debug-controlled reset.
|
||||
sys.reset := ResetCatchAndSync(clock, async_corerst, 20)
|
||||
Debug.connectDebugClockAndReset(sys.debug, clock)
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Check for unsupported rocket-chip connections
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
require (p(NExtTopInterrupts) == 0, "No Top-level interrupts supported");
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Build GPIO Pin Mux
|
||||
//-----------------------------------------------------------------------
|
||||
// Pin Mux for UART, SPI, PWM
|
||||
// First convert the System outputs into "IOF" using the respective *GPIOPort
|
||||
// converters.
|
||||
|
||||
val sys_uart = sys.uart
|
||||
val sys_pwm = sys.pwm
|
||||
val sys_spi = sys.spi
|
||||
val sys_i2c = sys.i2c
|
||||
|
||||
val uart_pins = p(PeripheryUARTKey).map { c => Wire(new UARTPins(() => PinGen()))}
|
||||
val pwm_pins = p(PeripheryPWMKey).map { c => Wire(new PWMPins(() => PinGen(), c))}
|
||||
val spi_pins = p(PeripherySPIKey).map { c => Wire(new SPIPins(() => PinGen(), c))}
|
||||
val i2c_pins = p(PeripheryI2CKey).map { c => Wire(new I2CPins(() => PinGen()))}
|
||||
|
||||
(uart_pins zip sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
|
||||
(pwm_pins zip sys_pwm) map {case (p, r) => PWMPinsFromPort(p, r) }
|
||||
(spi_pins zip sys_spi) map {case (p, r) => SPIPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
|
||||
(i2c_pins zip sys_i2c) map {case (p, r) => I2CPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Default Pin connections before attaching pinmux
|
||||
|
||||
for (iof_0 <- sys.gpio(0).iof_0.get) {
|
||||
iof_0.default()
|
||||
}
|
||||
|
||||
for (iof_1 <- sys.gpio(0).iof_1.get) {
|
||||
iof_1.default()
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
val iof_0 = sys.gpio(0).iof_0.get
|
||||
val iof_1 = sys.gpio(0).iof_1.get
|
||||
|
||||
// SPI1 (0 is the dedicated)
|
||||
BasePinToIOF(spi_pins(0).cs(0), iof_0(2))
|
||||
BasePinToIOF(spi_pins(0).dq(0), iof_0(3))
|
||||
BasePinToIOF(spi_pins(0).dq(1), iof_0(4))
|
||||
BasePinToIOF(spi_pins(0).sck, iof_0(5))
|
||||
BasePinToIOF(spi_pins(0).dq(2), iof_0(6))
|
||||
BasePinToIOF(spi_pins(0).dq(3), iof_0(7))
|
||||
BasePinToIOF(spi_pins(0).cs(1), iof_0(8))
|
||||
BasePinToIOF(spi_pins(0).cs(2), iof_0(9))
|
||||
BasePinToIOF(spi_pins(0).cs(3), iof_0(10))
|
||||
|
||||
// SPI2
|
||||
BasePinToIOF(spi_pins(1).cs(0), iof_0(26))
|
||||
BasePinToIOF(spi_pins(1).dq(0), iof_0(27))
|
||||
BasePinToIOF(spi_pins(1).dq(1), iof_0(28))
|
||||
BasePinToIOF(spi_pins(1).sck, iof_0(29))
|
||||
BasePinToIOF(spi_pins(1).dq(2), iof_0(30))
|
||||
BasePinToIOF(spi_pins(1).dq(3), iof_0(31))
|
||||
|
||||
// I2C
|
||||
if (p(PeripheryI2CKey).length == 1) {
|
||||
BasePinToIOF(i2c_pins(0).sda, iof_0(12))
|
||||
BasePinToIOF(i2c_pins(0).scl, iof_0(13))
|
||||
}
|
||||
|
||||
// UART0
|
||||
BasePinToIOF(uart_pins(0).rxd, iof_0(16))
|
||||
BasePinToIOF(uart_pins(0).txd, iof_0(17))
|
||||
|
||||
// UART1
|
||||
BasePinToIOF(uart_pins(1).rxd, iof_0(24))
|
||||
BasePinToIOF(uart_pins(1).txd, iof_0(25))
|
||||
|
||||
//PWM
|
||||
BasePinToIOF(pwm_pins(0).pwm(0), iof_1(0) )
|
||||
BasePinToIOF(pwm_pins(0).pwm(1), iof_1(1) )
|
||||
BasePinToIOF(pwm_pins(0).pwm(2), iof_1(2) )
|
||||
BasePinToIOF(pwm_pins(0).pwm(3), iof_1(3) )
|
||||
|
||||
BasePinToIOF(pwm_pins(1).pwm(1), iof_1(19))
|
||||
BasePinToIOF(pwm_pins(1).pwm(0), iof_1(20))
|
||||
BasePinToIOF(pwm_pins(1).pwm(2), iof_1(21))
|
||||
BasePinToIOF(pwm_pins(1).pwm(3), iof_1(22))
|
||||
|
||||
BasePinToIOF(pwm_pins(2).pwm(0), iof_1(10))
|
||||
BasePinToIOF(pwm_pins(2).pwm(1), iof_1(11))
|
||||
BasePinToIOF(pwm_pins(2).pwm(2), iof_1(12))
|
||||
BasePinToIOF(pwm_pins(2).pwm(3), iof_1(13))
|
||||
|
||||
//-----------------------------------------------------------------------
|
||||
// Drive actual Pads
|
||||
//-----------------------------------------------------------------------
|
||||
|
||||
// Result of Pin Mux
|
||||
GPIOPinsFromPort(io.pins.gpio, sys.gpio(0))
|
||||
|
||||
// Dedicated SPI Pads
|
||||
SPIPinsFromPort(io.pins.qspi, sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3)
|
||||
|
||||
// JTAG Debug Interface
|
||||
val sjtag = sys.debug.get.systemjtag.get
|
||||
JTAGPinsFromPort(io.pins.jtag, sjtag.jtag)
|
||||
sjtag.reset := io.jtag_reset
|
||||
sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
|
||||
|
||||
io.ndreset := sys.debug.get.ndreset
|
||||
|
||||
// AON Pads -- direct connection is OK because
|
||||
// EnhancedPin is hard-coded in MockAONPads
|
||||
// and thus there is no .fromPort method.
|
||||
io.pins.aon <> sys.aon.pins
|
||||
}
|
||||
51
fpga/src/main/scala/arty/System.scala
Normal file
51
fpga/src/main/scala/arty/System.scala
Normal file
@@ -0,0 +1,51 @@
|
||||
// See LICENSE for license details.
|
||||
package sifive.freedom.everywhere.e300artydevkit
|
||||
|
||||
import Chisel._
|
||||
|
||||
import freechips.rocketchip.config._
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.devices.debug._
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.system._
|
||||
|
||||
import sifive.blocks.devices.mockaon._
|
||||
import sifive.blocks.devices.gpio._
|
||||
import sifive.blocks.devices.pwm._
|
||||
import sifive.blocks.devices.spi._
|
||||
import sifive.blocks.devices.uart._
|
||||
import sifive.blocks.devices.i2c._
|
||||
|
||||
//-------------------------------------------------------------------------
|
||||
// E300ArtyDevKitSystem
|
||||
//-------------------------------------------------------------------------
|
||||
|
||||
class E300ArtyDevKitSystem(implicit p: Parameters) extends RocketSubsystem
|
||||
with HasPeripheryDebug
|
||||
with HasPeripheryMockAON
|
||||
with chipyard.example.CanHavePeripheryGCD
|
||||
with HasPeripheryUART
|
||||
with HasPeripherySPIFlash
|
||||
with HasPeripherySPI
|
||||
with HasPeripheryGPIO
|
||||
with HasPeripheryPWM
|
||||
with HasPeripheryI2C {
|
||||
override lazy val module = new E300ArtyDevKitSystemModule(this)
|
||||
}
|
||||
|
||||
class E300ArtyDevKitSystemModule[+L <: E300ArtyDevKitSystem](_outer: L)
|
||||
extends RocketSubsystemModuleImp(_outer)
|
||||
with HasPeripheryDebugModuleImp
|
||||
with chipyard.example.CanHavePeripheryGCDModuleImp
|
||||
with HasPeripheryUARTModuleImp
|
||||
with HasPeripherySPIModuleImp
|
||||
with HasPeripheryGPIOModuleImp
|
||||
with HasPeripherySPIFlashModuleImp
|
||||
with HasPeripheryMockAONModuleImp
|
||||
with HasPeripheryPWMModuleImp
|
||||
with HasPeripheryI2CModuleImp {
|
||||
// Reset vector is set to the location of the mask rom
|
||||
val maskROMParams = p(PeripheryMaskROMKey)
|
||||
global_reset_vector := maskROMParams(0).address.U
|
||||
}
|
||||
Reference in New Issue
Block a user