From a681bedae05fb9ae9d0d5302a9a4a5b3128eebf7 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Fri, 24 Feb 2023 20:37:36 -0800 Subject: [PATCH 1/5] fix top/model separation for rtl vs. post-syn/par sim --- vlsi/Makefile | 6 ++++++ vlsi/sim.mk | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index ab8438d5..97fba910 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -118,6 +118,12 @@ endif $(SYN_CONF): $(VLSI_RTL) mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " input_files:" >> $@ + for x in $(VLSI_RTL); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ echo "synthesis.inputs:" >> $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 5623f9d3..b487657c 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files) echo " top_module: $(VLSI_TOP)" >> $@ echo " tb_name: ''" >> $@ # don't specify -top echo " input_files:" >> $@ - for x in $$(cat $(sim_common_files)); do \ + for x in $$(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@ From c1e8b202347349a4f67a2d08679afb61b994e07d Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Mon, 27 Feb 2023 15:24:00 -0800 Subject: [PATCH 2/5] add SIM_FILE_REQS --- vlsi/sim.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/sim.mk b/vlsi/sim.mk index b487657c..13a7fcc3 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files) echo " top_module: $(VLSI_TOP)" >> $@ echo " tb_name: ''" >> $@ # don't specify -top echo " input_files:" >> $@ - for x in $$(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE); do \ + for x in $$(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@ From 89929cbb6eeac1a46ed39499ef8e79e4bd81aea1 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Tue, 28 Feb 2023 13:10:49 -0800 Subject: [PATCH 3/5] cat VLSI_RTL --- vlsi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index 97fba910..c31f7304 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -120,7 +120,7 @@ $(SYN_CONF): $(VLSI_RTL) mkdir -p $(dir $@) echo "sim.inputs:" > $@ echo " input_files:" >> $@ - for x in $(VLSI_RTL); do \ + for x in $$(cat $(VLSI_RTL)); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@ From 54c55875e169649f45f9ef3e47183df8507ba88b Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Fri, 3 Mar 2023 14:50:09 -0800 Subject: [PATCH 4/5] hierarchical flows should all fall under TOP suffix instead of VLSI_TOP which will change --- vlsi/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index c31f7304..8259e7a6 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -46,9 +46,9 @@ VLSI_MODEL_DUT_NAME ?= chiptop # If overriding, this should be relative to $(vlsi_dir) VLSI_OBJ_DIR ?= build ifneq ($(CUSTOM_VLOG),) - OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) + OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(VLSI_TOP) else - OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) + OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(TOP) endif ######################################################################################### From 08839930009a6f15f2b3ba73940c243d34750ab6 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 8 Mar 2023 16:11:01 -0800 Subject: [PATCH 5/5] model and top reference common modules, need to filter them out from sim to avoid module collisions --- vlsi/sim.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/sim.mk b/vlsi/sim.mk index 13a7fcc3..1f5b530d 100644 --- a/vlsi/sim.mk +++ b/vlsi/sim.mk @@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files) echo " top_module: $(VLSI_TOP)" >> $@ echo " tb_name: ''" >> $@ # don't specify -top echo " input_files:" >> $@ - for x in $$(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ + for x in $$(comm -23 <(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) <(sort $(VLSI_RTL))) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@