From aa057239f2bc14d4001681ae01e4ea759e1b4c2e Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 17 Oct 2023 14:38:28 -0700 Subject: [PATCH] Bump rocket-chip + submodules for new clustered-tile API --- fpga/fpga-shells | 2 +- generators/bar-fetchers | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/ChipTop.scala | 1 - .../chipyard/src/main/scala/DigitalTop.scala | 1 - .../chipyard/src/main/scala/SpikeTile.scala | 35 ++++++++++--------- .../chipyard/src/main/scala/Subsystem.scala | 28 ++++++++------- .../chipyard/src/main/scala/System.scala | 7 ---- .../chipyard/src/main/scala/TestSuites.scala | 2 +- .../main/scala/clocking/ClockBinders.scala | 25 ++----------- .../main/scala/clocking/HasChipyardPRCI.scala | 31 +++++----------- .../main/scala/config/AbstractConfig.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 8 +++++ .../main/scala/config/TracegenConfigs.scala | 2 +- .../config/fragments/ClockingFragments.scala | 4 +-- .../config/fragments/RoCCFragments.scala | 8 ++--- .../config/fragments/SubsystemFragments.scala | 4 +-- .../config/fragments/TileFragments.scala | 14 ++++---- .../src/main/scala/example/FlatChipTop.scala | 12 +------ .../chipyard/src/main/scala/example/GCD.scala | 2 +- .../src/main/scala/example/TutorialTile.scala | 19 +++++----- .../src/main/scala/iobinders/IOBinders.scala | 10 +++--- generators/cva6 | 2 +- .../firechip/src/main/scala/FireSim.scala | 8 ++--- generators/ibex | 2 +- generators/riscv-sodor | 2 +- generators/rocket-chip | 2 +- generators/shuttle | 2 +- generators/sifive-blocks | 2 +- generators/sifive-cache | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/Configs.scala | 18 +++++----- .../tracegen/src/main/scala/System.scala | 5 +-- 33 files changed, 116 insertions(+), 152 deletions(-) diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 2ce3e6f3..19e0e87c 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 2ce3e6f3df06d64c858bc1073ba1c75e7eb71a07 +Subproject commit 19e0e87cedd438f8231bb7af420cc58792735473 diff --git a/generators/bar-fetchers b/generators/bar-fetchers index a5bd985d..12d1506f 160000 --- a/generators/bar-fetchers +++ b/generators/bar-fetchers @@ -1 +1 @@ -Subproject commit a5bd985d29b07940e326d78964b370fa1cefec71 +Subproject commit 12d1506f610048906d2407b40a706923cbe6571e diff --git a/generators/boom b/generators/boom index 96da674b..65b0d39b 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 96da674bc97955e7fa068f0a9a1d0a7a479d1d0b +Subproject commit 65b0d39b35bb5dbb3deba826979c5145846648ae diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 150221b6..ec636dfb 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -5,7 +5,6 @@ import chisel3._ import scala.collection.mutable.{ArrayBuffer} import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup} -import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey} import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope} import freechips.rocketchip.util.{ResetCatchAndSync} diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index d7263008..1dafe42d 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -40,7 +40,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem } class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l) - with testchipip.CanHaveTraceIOModuleImp with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index fc822c22..7778deb6 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -77,14 +77,15 @@ case class SpikeTileAttachParams( } case class SpikeTileParams( - hartId: Int = 0, + tileId: Int = 0, val core: SpikeCoreParams = SpikeCoreParams(), icacheParams: ICacheParams = ICacheParams(nWays = 32), dcacheParams: DCacheParams = DCacheParams(nWays = 32), tcmParams: Option[MasterPortParams] = None // tightly coupled memory ) extends InstantiableTileParams[SpikeTile] { - val name = Some("spike_tile") + val baseName = "spike_tile" + val uniqueName = s"${baseName}_$tileId" val beuAddr = None val blockerCtrlAddr = None val btb = None @@ -92,7 +93,7 @@ case class SpikeTileParams( val dcache = Some(dcacheParams) val icache = Some(icacheParams) val clockSinkParams = ClockSinkParameters() - def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): SpikeTile = { + def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): SpikeTile = { new SpikeTile(this, crossing, lookup) } } @@ -106,11 +107,11 @@ class SpikeTile( with SourcesExternalNotifications { // Private constructor ensures altered LazyModule.p is used implicitly - def this(params: SpikeTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = + def this(params: SpikeTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) // Required TileLink nodes - val intOutwardNode = IntIdentityNode() + val intOutwardNode = Some(IntIdentityNode()) val masterNode = visibilityNode val slaveNode = TLIdentityNode() @@ -129,21 +130,21 @@ class SpikeTile( } ResourceBinding { - Resource(cpuDevice, "reg").bind(ResourceAddress(hartId)) + Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } val icacheNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( sourceId = IdRange(0, 1), - name = s"Core ${staticIdForMetadataUseOnly} ICache"))))) + name = s"Core ${tileId} ICache"))))) val dcacheNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( - name = s"Core ${staticIdForMetadataUseOnly} DCache", + name = s"Core ${tileId} DCache", sourceId = IdRange(0, tileParams.dcache.get.nMSHRs), supportsProbe = TransferSizes(p(CacheBlockBytes), p(CacheBlockBytes))))))) val mmioNode = TLClientNode((Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1( - name = s"Core ${staticIdForMetadataUseOnly} MMIO", + name = s"Core ${tileId} MMIO", sourceId = IdRange(0, 1), requestFifo = true)))))) @@ -313,7 +314,7 @@ class SpikeBlackBox( } class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { - + val tileParams = outer.tileParams // We create a bundle here and decode the interrupt. val int_bundle = Wire(new TileInterrupts()) outer.decodeCoreInterrupts(int_bundle) @@ -337,7 +338,7 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { // then the DTM-based bringup with SimDTM will be used. This isn't required to be // true, but it usually is val useDTM = p(ExportDebug).protocols.contains(DMI) - val spike = Module(new SpikeBlackBox(hartId, isaDTS, tileParams.core.nPMPs, + val spike = Module(new SpikeBlackBox(outer.tileId, outer.isaDTS, tileParams.core.nPMPs, tileParams.icache.get.nSets, tileParams.icache.get.nWays, tileParams.dcache.get.nSets, tileParams.dcache.get.nWays, tileParams.dcache.get.nMSHRs, @@ -467,19 +468,21 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) { } } -class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams(), - overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => { +class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams() +) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { // Calculate the next available hart ID (since hart ID cannot be duplicated) val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) // Create TileAttachParams for every core to be instantiated (0 until n).map { i => SpikeTileAttachParams( - tileParams = tileParams.copy(hartId = i + idOffset) + tileParams = tileParams.copy(tileId = i + idOffset) ) } ++ prev } + case NumTiles => up(NumTiles) + n + }) class WithSpikeTCM extends Config((site, here, up) => { @@ -492,5 +495,5 @@ class WithSpikeTCM extends Config((site, here, up) => { ))) } case ExtMem => None - case BankedL2Key => up(BankedL2Key).copy(nBanks = 0) + case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey).copy(nBanks = 0) }) diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index d25d4fa3..1a41ce81 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -71,18 +71,24 @@ trait CanHaveChosenInDTS { this: BaseSubsystem => } class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem - with HasTiles - with HasPeripheryDebug - with CanHaveHTIF - with CanHaveChosenInDTS + with InstantiatesHierarchicalElements + with HasTileNotificationSinks + with HasTileInputConstants + with CanHavePeripheryCLINT + with CanHavePeripheryPLIC + with HasPeripheryDebug + with HasHierarchicalElementsRootContext + with HasHierarchicalElements + with CanHaveHTIF + with CanHaveChosenInDTS { - def coreMonitorBundles = tiles.map { + def coreMonitorBundles = totalTiles.values.map { case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle case b: BoomTile => b.module.core.coreMonitorBundle }.toList // No-tile configs have to be handled specially. - if (tiles.size == 0) { + if (totalTiles.size == 0) { // no PLIC, so sink interrupts to nowhere require(!p(PLICKey).isDefined) val intNexus = IntNexusNode(sourceFn = x => x.head, sinkFn = x => x.head) @@ -96,10 +102,6 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem tileHaltXbarNode := IntSourceNode(IntSourcePortSimple()) tileWFIXbarNode := IntSourceNode(IntSourcePortSimple()) tileCeaseXbarNode := IntSourceNode(IntSourcePortSimple()) - - // Sink reset vectors to nowhere - val resetVectorSink = BundleBridgeSink[UInt](Some(() => UInt(28.W))) - resetVectorSink := tileResetVectorNode } // Relying on [[TLBusWrapperConnection]].driveClockFromMaster for @@ -107,7 +109,7 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem // ClockGroup. This makes it impossible to determine which clocks are driven // by which bus based on the member names, which is problematic when there is // a rational crossing between two buses. Instead, provide all bus clocks - // directly from the asyncClockGroupsNode in the subsystem to ensure bus + // directly from the allClockGroupsNode in the subsystem to ensure bus // names are always preserved in the top-level clock names. // // For example, using a RationalCrossing between the Sbus and Cbus, and @@ -116,12 +118,12 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem // Conversly, if an async crossing is used, they instead receive names of the // form "subsystem_cbus_[0-9]*". The assignment below provides the latter names in all cases. Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc => - tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode } + tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := allClockGroupsNode } } override lazy val module = new ChipyardSubsystemModuleImp(this) } class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) - with HasTilesModuleImp + with HasHierarchicalElementsRootContextModuleImp { } diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 5643e380..b8a04eac 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -32,13 +32,6 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) } val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) } - // If there is no bootrom, the tile reset vector bundle will be tied to zero - if (bootROM.isEmpty) { - val fakeResetVectorSourceNode = BundleBridgeSource[UInt]() - InModuleBody { fakeResetVectorSourceNode.bundle := 0.U } - tileResetVectorNexusNode := fakeResetVectorSourceNode - } - override lazy val module = new ChipyardSystemModule(this) } diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 0e4e3310..2a88ebb2 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -65,7 +65,7 @@ class TestSuiteHelper */ def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = { val xlen = p(XLen) - tiles.find(_.hartId == 0).map { tileParams => + tiles.find(_.tileId == 0).map { tileParams => val coreParams = tileParams.core val vm = coreParams.useVM val env = if (vm) List("p","v") else List("p") diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 3ef8a61b..fa31163d 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -18,16 +18,6 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { // Connect the implicit clock implicit val p = GetSystemParameters(system) - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - InModuleBody { - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - } val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere) val baseAddress = system.prciParams.baseAddress val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) } @@ -38,7 +28,7 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get } - system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode + system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode // Connect all other requested clocks val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) @@ -83,23 +73,12 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ // This passes all clocks through to the TestHarness class WithPassthroughClockGenerator extends OverrideLazyIOBinder({ (system: HasChipyardPRCI) => { - // Connect the implicit clock implicit val p = GetSystemParameters(system) - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - InModuleBody { - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - } // This aggregate node should do nothing val clockGroupAggNode = ClockGroupAggregateNode("fake") val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters())) - system.allClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode + system.chiptopClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode InModuleBody { val reset_io = IO(Input(AsyncReset())) diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala index 356a0432..a9832806 100644 --- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala +++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala @@ -29,8 +29,8 @@ case class ChipyardPRCIControlParams( case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) -trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => - require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven") +trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElementss => + require(!p(SubsystemDriveDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) @@ -48,29 +48,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node - val allClockGroupsNode = ClockGroupEphemeralNode() - // There are two "sets" of clocks which must be dealt with - - // 1. The implicit clock from the subsystem. RC is moving away from depending on this - // clock, but some modules still use it. Since the implicit clock sink node - // is created in the ChipTop (the hierarchy wrapping the subsystem), this function - // is provided to allow connecting that clock to the clock aggregator. This function - // should be called in the ChipTop context - def connectImplicitClockSinkNode(sink: ClockSinkNode) = { - val implicitClockGrouper = this { ClockGroup() } - (sink - := implicitClockGrouper - := aggregator) - } - - // 2. The rest of the diplomatic clocks in the subsystem are routed to this asyncClockGroupsNode + // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() - (asyncClockGroupsNode + (allClockGroupsNode :*= clockNamePrefixer :*= aggregator) - // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) @@ -91,7 +75,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles => } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, - tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil)) + tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get reset_setter } } @@ -115,11 +99,14 @@ RTL SIMULATORS, NAMELY VERILATOR. """ + Console.RESET) } + // The chiptopClockGroupsNode shouuld be what ClockBinders attach to + val chiptopClockGroupsNode = ClockGroupEphemeralNode() + (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) - := allClockGroupsNode) + := chiptopClockGroupsNode) } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index a08abb6d..0891a21d 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -66,7 +66,7 @@ class AbstractConfig extends Config( new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks + new chipyard.config.WithNoSubsystemClockIO ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index c45fb6f2..a9f87b28 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -2,6 +2,7 @@ package chipyard import org.chipsalliance.cde.config.{Config} import freechips.rocketchip.diplomacy.{AsynchronousCrossing} +import freechips.rocketchip.subsystem.{InCluster} // -------------- // Rocket Configs @@ -110,3 +111,10 @@ class PrefetchingRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++ // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) + +class ClusteredRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(1)) ++ + new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(0)) ++ + new freechips.rocketchip.subsystem.WithCluster(1) ++ + new freechips.rocketchip.subsystem.WithCluster(0) ++ + new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 55cce1b8..78c815fb 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -14,7 +14,7 @@ class AbstractTraceGenConfig extends Config( new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++ new chipyard.config.WithTracegenSystem ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ + new chipyard.config.WithNoSubsystemClockIO ++ new chipyard.config.WithMemoryBusFrequency(1000.0) ++ new chipyard.config.WithSystemBusFrequency(1000.0) ++ new chipyard.config.WithPeripheryBusFrequency(1000.0) ++ diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 2da9fbf2..8ccc8afa 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -18,8 +18,8 @@ import chipyard.clocking._ // with the implicit clocks of Subsystem. Don't do that, instead we extend // the diplomacy graph upwards into the ChipTop, where we connect it to // our clock drivers -class WithNoSubsystemDrivenClocks extends Config((site, here, up) => { - case SubsystemDriveAsyncClockGroupsKey => None +class WithNoSubsystemClockIO extends Config((site, here, up) => { + case SubsystemDriveClockGroupsFromIO => false }) /** diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala index 4680eeeb..c9f7fcdb 100644 --- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala @@ -12,15 +12,15 @@ import gemmini._ import chipyard.{TestSuitesKey, TestSuiteHelper} /** - * Map from a hartId to a particular RoCC accelerator + * Map from a tileId to a particular RoCC accelerator */ case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]]) /** - * Config fragment to enable different RoCCs based on the hartId + * Config fragment to enable different RoCCs based on the tileId */ class WithMultiRoCC extends Config((site, here, up) => { - case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil) + case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).tileId, Nil) }) /** @@ -39,7 +39,7 @@ class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) => * * For ex: * Core 0, 1, 2, 3 have been defined earlier - * with hartIds of 0, 1, 2, 3 respectively + * with tileIds of 0, 1, 2, 3 respectively * And you call WithMultiRoCCHwacha(0,1) * Then Core 0 and 1 will get a Hwacha * diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index 40f18d5d..4416a572 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -1,12 +1,12 @@ package chipyard.config import org.chipsalliance.cde.config.{Config} -import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper} +import freechips.rocketchip.subsystem.{SystemBusKey, SubsystemBankedCoherenceKey, CoherenceManagerWrapper} import freechips.rocketchip.diplomacy.{DTSTimebase} // Replaces the L2 with a broadcast manager for maintaining coherence class WithBroadcastManager extends Config((site, here, up) => { - case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) + case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager) }) class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala index 17eaa3f0..db104867 100644 --- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala @@ -69,7 +69,7 @@ class WithNPMPs(n: Int = 8) extends Config((site, here, up) => { class WithRocketICacheScratchpad extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - icache = tp.tileParams.icache.map(_.copy(itimAddr = Some(0x300000 + tp.tileParams.hartId * 0x10000))) + icache = tp.tileParams.icache.map(_.copy(itimAddr = Some(0x300000 + tp.tileParams.tileId * 0x10000))) )) } }) @@ -77,7 +77,7 @@ class WithRocketICacheScratchpad extends Config((site, here, up) => { class WithRocketDCacheScratchpad extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - dcache = tp.tileParams.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + tp.tileParams.hartId * 0x10000))) + dcache = tp.tileParams.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + tp.tileParams.tileId * 0x10000))) )) } }) @@ -85,14 +85,14 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => { class WithTilePrefetchers extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master))) + master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master))) } }) diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index a1a1aeaa..954deec8 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -24,9 +24,6 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { //======================== // Diplomatic clock stuff //======================== - val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock")))) - system.connectImplicitClockSinkNode(implicitClockSinkNode) - val tlbus = system.locateTLBusWrapper(system.prciParams.slaveWhere) val baseAddress = system.prciParams.baseAddress val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) } @@ -37,7 +34,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } - system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode + system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode // Connect all other requested clocks val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters())) @@ -61,13 +58,6 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { //========================= // Clock/reset //========================= - val implicit_clock = implicitClockSinkNode.in.head._1.clock - val implicit_reset = implicitClockSinkNode.in.head._1.reset - system.module match { case l: LazyModuleImp => { - l.clock := implicit_clock - l.reset := implicit_reset - }} - val clock_wire = Wire(Input(Clock())) val reset_wire = Wire(Input(AsyncReset())) val (clock_pad, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey)) diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index 5e6c5d67..a92beb55 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -185,7 +185,7 @@ trait CanHavePeripheryGCD { this: BaseSubsystem => // DOC include end: GCD lazy trait // DOC include start: GCD imp trait -trait CanHavePeripheryGCDModuleImp extends LazyModuleImp { +trait CanHavePeripheryGCDModuleImp extends LazyRawModuleImp { val outer: CanHavePeripheryGCD val gcd_busy = outer.gcd match { case Some(gcd) => { diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 38c8577a..54be0f8a 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -82,7 +82,7 @@ case class MyTileAttachParams( case class MyTileParams( name: Option[String] = Some("my_tile"), - hartId: Int = 0, + tileId: Int = 0, trace: Boolean = false, val core: MyCoreParams = MyCoreParams() ) extends InstantiableTileParams[MyTile] @@ -94,9 +94,11 @@ case class MyTileParams( val dcache: Option[DCacheParams] = Some(DCacheParams()) val icache: Option[ICacheParams] = Some(ICacheParams()) val clockSinkParams: ClockSinkParameters = ClockSinkParameters() - def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = { + def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = { new MyTile(this, crossing, lookup) } + val baseName = name.getOrElse("my_tile") + val uniqueName = s"${baseName}_$tileId" } // DOC include start: Tile class @@ -111,11 +113,11 @@ class MyTile( { // Private constructor ensures altered LazyModule.p is used implicitly - def this(params: MyTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = + def this(params: MyTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) // Require TileLink nodes - val intOutwardNode = IntIdentityNode() + val intOutwardNode = Some(IntIdentityNode()) val masterNode = visibilityNode val slaveNode = TLIdentityNode() @@ -135,7 +137,7 @@ class MyTile( } ResourceBinding { - Resource(cpuDevice, "reg").bind(ResourceAddress(hartId)) + Resource(cpuDevice, "reg").bind(ResourceAddress(tileId)) } // TODO: Create TileLink nodes and connections here. @@ -228,15 +230,15 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){ } // DOC include start: Config fragment -class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => { +class WithNMyCores(n: Int = 1) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { // Calculate the next available hart ID (since hart ID cannot be duplicated) val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) // Create TileAttachParams for every core to be instantiated (0 until n).map { i => MyTileAttachParams( - tileParams = MyTileParams(hartId = i + idOffset), + tileParams = MyTileParams(tileId = i + idOffset), crossingParams = RocketCrossingParams() ) } ++ prev @@ -245,5 +247,6 @@ class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Con case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8) // The # of instruction bits. Use maximum # of bits if your core supports both 32 and 64 bits. case XLen => 64 + case NumTiles => up(NumTiles) + n }) // DOC include end: Config fragment diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 773f3d39..7fdc2a37 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -453,14 +453,14 @@ class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({ } }) -class WithTraceIOPunchthrough extends OverrideIOBinder({ - (system: CanHaveTraceIOModuleImp) => { +class WithTraceIOPunchthrough extends OverrideLazyIOBinder({ + (system: CanHaveTraceIO) => InModuleBody { val ports: Option[TracePort] = system.traceIO.map { t => val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace") trace <> t val p = GetSystemParameters(system) val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem] - val tiles = chipyardSystem.tiles + val tiles = chipyardSystem.totalTiles.values val cfg = SpikeCosimConfig( isa = tiles.headOption.map(_.isaDTS).getOrElse(""), vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0), @@ -509,8 +509,8 @@ class WithDontTouchPorts extends OverrideIOBinder({ }) class WithNMITiedOff extends ComposeIOBinder({ - (system: HasTilesModuleImp) => { - system.nmi.flatten.foreach { nmi => + (system: HasHierarchicalElementsRootContextModuleImp) => { + system.nmi.foreach { nmi => nmi.rnmi := false.B nmi.rnmi_interrupt_vector := 0.U nmi.rnmi_exception_vector := 0.U diff --git a/generators/cva6 b/generators/cva6 index 46323fcd..942d5aef 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 46323fcd7407544c751b353f52e356eb8f33e9d1 +Subproject commit 942d5aef13ab82ce12adfd5346b2a2716832d69d diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 4cca7557..599788bc 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -8,7 +8,7 @@ import chisel3._ import chisel3.experimental.{IO, annotate} import freechips.rocketchip.prci._ -import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey, HasTiles} +import freechips.rocketchip.subsystem._ import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName} import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap} @@ -103,8 +103,8 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta // FireSim ModelMultithreading chiptops.foreach { case c: ChipTop => c.lazySystem match { - case ls: HasTiles => { - if (p(FireSimMultiCycleRegFile)) ls.tiles.map { + case ls: InstantiatesHierarchicalElements => { + if (p(FireSimMultiCycleRegFile)) ls.totalTiles.values.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) @@ -120,7 +120,7 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta } case _ => } - if (p(FireSimFAME5)) ls.tiles.map { + if (p(FireSimFAME5)) ls.totalTiles.values.map { case b: BoomTile => annotate(EnableModelMultiThreadingAnnotation(b.module)) case r: RocketTile => diff --git a/generators/ibex b/generators/ibex index 66ec6e56..b52a2d72 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 66ec6e56ed69df4e4af5383128cf21adf88b08fc +Subproject commit b52a2d721993d7b38982a0fa62b696798ac4dd9a diff --git a/generators/riscv-sodor b/generators/riscv-sodor index c1c809eb..ebb45b94 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit c1c809ebd5c9a76cd60d8c3169cea4bf4b2fa8fd +Subproject commit ebb45b9439a19e2710ce0f2ee6e9ae2a192cbddf diff --git a/generators/rocket-chip b/generators/rocket-chip index 50adbdb3..e0ea9034 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 50adbdb3e4e18c2b3de57693323f4174b60f9767 +Subproject commit e0ea90344e9edb6a4e24f84e7729d83c217c8859 diff --git a/generators/shuttle b/generators/shuttle index e628836c..924d269d 160000 --- a/generators/shuttle +++ b/generators/shuttle @@ -1 +1 @@ -Subproject commit e628836c3c4bfe29927cd9e1473801fab33dee6c +Subproject commit 924d269d1ef81adfeb263a3d898c82105f7d50ed diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 5edd72e7..212c7b07 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 5edd72e793ccb534b1395d0d8c1831754fd72fec +Subproject commit 212c7b070bc7132f31a26deec6b2bde9e0b1b612 diff --git a/generators/sifive-cache b/generators/sifive-cache index 51d400bd..bcd248a2 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 51d400bd32131e8914c6713bfb71bef690f2fe70 +Subproject commit bcd248a2a2e86084a136c05d1844d88d9fba18e5 diff --git a/generators/testchipip b/generators/testchipip index 6436959d..24de6bca 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6436959d997d0bb578790d95078648b478ca049b +Subproject commit 24de6bca032e730749535a75b37b30834cb23c28 diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala index 5d4f0211..f51052c5 100644 --- a/generators/tracegen/src/main/scala/Configs.scala +++ b/generators/tracegen/src/main/scala/Configs.scala @@ -13,19 +13,18 @@ import scala.math.{max, min} class WithTraceGen( n: Int = 2, - overrideIdOffset: Option[Int] = None, overrideMemOffset: Option[BigInt] = None)( params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) }, nReqs: Int = 8192 ) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) params.zipWithIndex.map { case (dcp, i) => TraceGenTileAttachParams( tileParams = TraceGenParams( - hartId = i + idOffset, + tileId = i + idOffset, dcache = Some(dcp), wordBits = site(XLen), addrBits = 48, @@ -48,23 +47,23 @@ class WithTraceGen( ) } ++ prev } + case NumTiles => up(NumTiles) + n }) class WithBoomTraceGen( n: Int = 2, - overrideIdOffset: Option[Int] = None, overrideMemOffset: Option[BigInt] = None)( params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) }, nReqs: Int = 8192 ) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) params.zipWithIndex.map { case (dcp, i) => BoomTraceGenTileAttachParams( tileParams = BoomTraceGenParams( - hartId = i + idOffset, + tileId = i + idOffset, dcache = Some(dcp), wordBits = site(XLen), addrBits = 48, @@ -84,24 +83,24 @@ class WithBoomTraceGen( ) } ++ prev } + case NumTiles => up(NumTiles) + n }) class WithL2TraceGen( n: Int = 2, - overrideIdOffset: Option[Int] = None, overrideMemOffset: Option[BigInt] = None)( params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) }, nReqs: Int = 8192 ) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => { val prev = up(TilesLocated(InSubsystem), site) - val idOffset = overrideIdOffset.getOrElse(prev.size) + val idOffset = up(NumTiles) val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L) params.zipWithIndex.map { case (dcp, i) => TraceGenTileAttachParams( tileParams = TraceGenParams( - hartId = i + idOffset, + tileId = i + idOffset, dcache = Some(dcp), wordBits = site(XLen), addrBits = 48, @@ -126,4 +125,5 @@ class WithL2TraceGen( ) } ++ prev } + case NumTiles => up(NumTiles) + n }) diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index 2a0ba3d5..5d3953cb 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -9,11 +9,12 @@ import freechips.rocketchip.subsystem._ import boom.lsu.BoomTraceGenTile class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem - with HasTiles + with InstantiatesHierarchicalElements + with HasTileNotificationSinks with CanHaveMasterAXI4MemPort { def coreMonitorBundles = Nil - val tileStatusNodes = tiles.collect { + val tileStatusNodes = totalTiles.values.toSeq.collect { case t: GroundTestTile => t.statusNode.makeSink() case t: BoomTraceGenTile => t.statusNode.makeSink() }