wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

remove extra newlines

Browse Source
This commit is contained in:
Sagar Karandikar
2023-05-10 11:31:05 -07:00
parent 95da9cefb5
commit abe8a7fb8b
1 changed files with 0 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -194,7 +194,6 @@ class FireSimRocketMMIOOnly1GiBDRAMConfig extends Config(
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 1L) ++
new FireSimRocketMMIOOnlyConfig)
class FireSimRocket4GiBDRAMConfig extends Config(
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++
new FireSimRocketConfig)
@@ -203,8 +202,6 @@ class FireSimRocketMMIOOnly4GiBDRAMConfig extends Config(
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++
new FireSimRocketMMIOOnlyConfig)
class FireSimQuadRocketConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++