From ad3188bca2e47e097d25d097d4c66cda63eef741 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Wed, 28 Sep 2022 17:06:53 -0700 Subject: [PATCH] improved example-designs override --- vlsi/example-designs/sky130-openroad.yml | 149 +---------------------- vlsi/tutorial.mk | 44 +++---- 2 files changed, 24 insertions(+), 169 deletions(-) diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml index 9b69972a..7c8a4e5c 100644 --- a/vlsi/example-designs/sky130-openroad.yml +++ b/vlsi/example-designs/sky130-openroad.yml @@ -1,152 +1,7 @@ # Override configurations in ../example-sky130.yml # Specify clock signals +# Relax the clock period for OpenROAD to meet timing vlsi.inputs.clocks: [ - {name: "clock_clock", period: "10ns", uncertainty: "1ns"} + {name: "clock_clock", period: "30ns", uncertainty: "1ns"} ] - -# # Power Straps -# par.power_straps_mode: generate -# par.generate_power_straps_method: by_tracks -# par.blockage_spacing: 40.0 -# par.blockage_spacing_top_layer: met4 -# par.generate_power_straps_options: -# by_tracks: -# strap_layers: -# - met4 -# - met5 -# pin_layers: -# - met5 -# blockage_spacing_met2: 4.0 -# blockage_spacing_met4: 2.0 -# blockage_spacing_met4: 2.0 -# track_width: 3 -# track_width_met5: 1 -# track_spacing: 5 -# track_start: 10 -# track_start_met5: 1 -# power_utilization: 0.1 -# power_utilization_met4: 0.1 -# power_utilization_met5: 0.1 - -# Placement Constraints -vlsi.inputs.placement_constraints: - - path: "ChipTop" - type: toplevel - x: 0 - y: 0 - width: 3500 - height: 2500 - margins: - left: 10 - right: 10 - top: 10 - bottom: 10 - - # # Place data cache SRAM instances - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0" - # type: hardmacro - # x: 50 - # y: 100 - # orientation: r0 - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0" - # type: hardmacro - # x: 50 - # y: 700 - # orientation: r0 - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0" - # type: hardmacro - # x: 50 - # y: 1300 - # orientation: r0 - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0" - # type: hardmacro - # x: 50 - # y: 1900 - # orientation: r0 - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0" - # type: hardmacro - # x: 1000 - # y: 1900 - # orientation: r0 - - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0" - # type: hardmacro - # x: 1000 - # y: 1300 - # orientation: r0 - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0" - # type: hardmacro - # x: 1000 - # y: 700 - # orientation: r0 - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0" - # type: hardmacro - # x: 1000 - # y: 100 - # orientation: r0 - - # # Place instruction cache SRAM instances - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0" - # type: hardmacro - # x: 3250 - # y: 100 - # orientation: r0 - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0" - # type: hardmacro - # x: 3250 - # y: 700 - # orientation: r0 - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0" - # type: hardmacro - # x: 3450 - # y: 1300 - # orientation: r0 - - # Place L2 TLB SRAM instances - # for some reason these don't remain SRAMs in the Yosys synthesis - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_0" - # type: hardmacro - # x: 2000 - # y: 1300 - # orientation: "r0" - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_1" - # type: hardmacro - # x: 2000 - # y: 1900 - # orientation: "r0" - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_2" - # type: hardmacro - # x: 2750 - # y: 1300 - # orientation: "r0" - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_3" - # type: hardmacro - # x: 2750 - # y: 1900 - # orientation: "r0" - - # - path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.ptw/l2_tlb_ram.l2_tlb_ram_ext.mem_0_4" - # type: hardmacro - # x: 3460 - # y: 1900 - # orientation: "r0" - -# # Override pin placement constraints -# vlsi.inputs.pin_mode: generated -# vlsi.inputs.pin.generate_mode: semi_auto -# vlsi.inputs.pin.assignments: [ -# {pins: "*", layers: ["met2", "met4"], side: "bottom"} -# ] diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index c85619e2..1fcd98ef 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -5,32 +5,32 @@ tutorial ?= none # TODO: eventually have asap7 commercial/openroad tutorial flavors ifeq ($(tutorial),asap7) - tech_name ?= asap7 - CONFIG ?= TinyRocketConfig - TOOLS_CONF ?= example-tools.yml - TECH_CONF ?= example-asap7.yml - INPUT_CONFS ?= $(EXTRA_CONFS) $(TOOLS_CONF) $(TECH_CONF) - VLSI_OBJ_DIR ?= build-asap7-commercial + tech_name ?= asap7 + CONFIG ?= TinyRocketConfig + TOOLS_CONF ?= example-tools.yml + TECH_CONF ?= example-asap7.yml + INPUT_CONFS ?= $(EXTRA_CONFS) $(TOOLS_CONF) $(TECH_CONF) + VLSI_OBJ_DIR ?= build-asap7-commercial endif ifeq ($(tutorial),sky130-commercial) - tech_name ?= sky130 - CONFIG ?= TinyRocketConfig - TOOLS_CONF ?= example-tools.yml - TECH_CONF ?= example-sky130.yml - DESIGN_CONF ?= example-designs/sky130-commercial.yml - EXTRA_CONFS ?= $(if $(filter $(TOP),Rocket RocketTile), example-designs/sky130-rocket.yml, ) - INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) - VLSI_OBJ_DIR ?= build-sky130-commercial + tech_name ?= sky130 + CONFIG ?= TinyRocketConfig + TOOLS_CONF ?= example-tools.yml + TECH_CONF ?= example-sky130.yml + DESIGN_CONF ?= example-designs/sky130-commercial.yml + EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, ) + INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) + VLSI_OBJ_DIR ?= build-sky130-commercial endif ifeq ($(tutorial),sky130-openroad) - tech_name ?= sky130 - CONFIG ?= TinyRocketConfig - TOOLS_CONF ?= example-openroad.yml - TECH_CONF ?= example-sky130.yml - DESIGN_CONF ?= example-designs/sky130-openroad.yml - EXTRA_CONFS ?= $(if $(filter $(TOP),Rocket RocketTile), example-designs/sky130-rocket.yml, ) - INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) - VLSI_OBJ_DIR ?= build-sky130-openroad + tech_name ?= sky130 + CONFIG ?= TinyRocketConfig + TOOLS_CONF ?= example-openroad.yml + TECH_CONF ?= example-sky130.yml + DESIGN_CONF ?= example-designs/sky130-openroad.yml + EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, ) + INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) + VLSI_OBJ_DIR ?= build-sky130-openroad endif