diff --git a/vlsi/Makefile b/vlsi/Makefile
index b7b56ee5..683c5e08 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -19,7 +19,7 @@ include $(base_dir)/variables.mk
 # vlsi types and rules
 #########################################################################################
 sim_name           ?= vcs # needed for GenerateSimFiles, but is unused
-tech_name          ?= asap7
+tech_name          ?= intech22
 tech_dir           ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\
                         $(shell python3 -c "import os, hammer.technology.$(tech_name);\
 						print(os.path.dirname(hammer.technology.$(tech_name).__file__))"),\
@@ -35,9 +35,9 @@ else
 endif
 
 ENV_YML            ?= $(vlsi_dir)/env.yml
-TECH_CONF          ?= example-$(tech_name).yml
+TECH_CONF          ?= $(tech_name).yml
 TOOLS_CONF         ?= example-tools.yml
-INPUT_CONFS        ?= $(TOOLS_CONF) $(TECH_CONF)
+INPUT_CONFS        ?= $(TOOLS_CONF) $(TECH_CONF) example-design.yml
 HAMMER_EXEC        ?= $(if $(filter $(tech_name),sky130),\
                         ./example-vlsi-sky130,\
                         ./example-vlsi)
@@ -86,8 +86,9 @@ else
 ifneq ($(EXT_FILELISTS),)
 	cat $(EXT_FILELISTS) >> $(VLSI_RTL)
 endif
+	./make_syn_f.sh $(build_dir)
+	
 endif
-	$(vlsi_dir)/make_syn_f.sh $(build_dir)
 
 #########################################################################################
 # srams
diff --git a/vlsi/add.mems.conf b/vlsi/add.mems.conf
index 41daece0..3580dde9 100644
--- a/vlsi/add.mems.conf
+++ b/vlsi/add.mems.conf
@@ -3,3 +3,4 @@ name dcache_tags depth 16 width 24 ports write,read
 name cache_mshr depth 8 width 305 ports write,read 
 name icache_data depth 128 width 1024 ports mwrite,read mask_gran 8 
 name icache_tags depth 128 width 21 ports write,read 
+name rf_bank depth 64 width 32 ports write,read 
diff --git a/vlsi/sim.mk b/vlsi/sim.mk
index 0e9d5675..34719765 100644
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -13,7 +13,7 @@ $(SIM_CONF): $(sim_common_files) check-binary
 	echo "  tb_name: ''" >> $@  # don't specify -top
 	echo "  input_files:" >> $@
 	# plusarg_reader is bugged, TODO perhaps raise the issue again in chipyard #1388 and #1442
-	for x in $$(cat $(MODEL_MODS_FILELIST) | grep -v cpp | sort -u) $(GEN_COLLATERAL_DIR)/plusarg_reader.v $(GEN_COLLATERAL_DIR)/GenericDeserializer.sv $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
+	for x in $$(cat $(MODEL_MODS_FILELIST) | grep -v cpp | sort -u) $(GEN_COLLATERAL_DIR)/plusarg_reader.v $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  input_files_meta: 'append'" >> $@