From aef7cda172874b758bd906e85a001b62c66525d5 Mon Sep 17 00:00:00 2001 From: Lux Date: Wed, 24 Jan 2024 17:24:59 -0800 Subject: [PATCH] removing seemingly useless override --- generators/chipyard/src/main/scala/example/GCD.scala | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index 3ed202ac..ef3edc1f 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -90,12 +90,7 @@ class GCDMMIOChiselModule(val w: Int) extends Module { // DOC include start: GCD router class GCDTL(params: GCDParams, beatBytes: Int)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) { - val device = new SimpleDevice("gcd", Seq("ucbbar,gcd")) { - override def describe(resources: ResourceBindings): Description = { - val Description(name, mapping) = super.describe(resources) - Description(name, mapping) - } - } + val device = new SimpleDevice("gcd", Seq("ucbbar,gcd")) val node = TLRegisterNode(Seq(AddressSet(params.address, 4096-1)), device, "reg/control", beatBytes=beatBytes) override lazy val module = new GCDImpl