From afff9c4243371af924904b02a0b8ead4b19da956 Mon Sep 17 00:00:00 2001
From: joonho hwangbo <joonho.whangbo@berkeley.edu>
Date: Wed, 15 May 2024 23:56:06 -0700
Subject: [PATCH] Misc configs | rocketchip bump (#1877)

* Misc configs | rocketchip bump

* Add NoTraceIOBridge

* Nit

* Remove useless configs

* FireSim NoC config
---
 .../src/main/scala/config/NoCConfigs.scala    | 23 +++++++++++++++++++
 .../src/main/scala/config/RocketConfigs.scala |  4 ++++
 .../src/main/scala/TargetConfigs.scala        |  8 ++++++-
 generators/rocket-chip                        |  2 +-
 4 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
index a5acc1e0..ac24d85c 100644
--- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
@@ -267,3 +267,26 @@ class SbusMeshNoCConfig extends Config(
   new chipyard.config.AbstractConfig
 )
 
+class QuadRocketSbusRingNoCConfig extends Config(
+  new constellation.soc.WithSbusNoC(constellation.protocol.SimpleTLNoCParams(
+    constellation.protocol.DiplomaticNetworkNodeMapping(
+      inNodeMapping = ListMap(
+        "Core 0 " -> 0,
+        "Core 1 " -> 1,
+        "Core 2 " -> 2,
+        "Core 3 " -> 3,
+        "serial_tl" -> 4),
+      outNodeMapping = ListMap(
+        "system[0]" -> 5,
+        "system[1]" -> 6,
+        "system[2]" -> 7,
+        "system[3]" -> 8,
+        "pbus" -> 4)), // TSI is on the pbus, so serial-tl and pbus should be on the same node
+    nocParams = NoCParams(
+      topology        = UnidirectionalTorus1D(9),
+      channelParamGen = (a, b) => UserChannelParams(Seq.fill(10) { UserVirtualChannelParams(4) }),
+      routingRelation = NonblockingVirtualSubnetworksRouting(UnidirectionalTorus1DDatelineRouting(), 5, 2))
+  )) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(4) ++
+  new freechips.rocketchip.subsystem.WithNBanks(4) ++
+  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index d3f21584..680129a3 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -12,6 +12,10 @@ class RocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
 
+class DualRocketConfig extends Config(
+  new freechips.rocketchip.subsystem.WithNBigCores(2) ++
+  new chipyard.config.AbstractConfig)
+
 class TinyRocketConfig extends Config(
   new chipyard.harness.WithDontTouchChipTopPorts(false) ++        // TODO FIX: Don't dontTouch the ports
   new testchipip.soc.WithNoScratchpads ++                         // All memory is the Rocket TCMs
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 8533d80b..42f0b1d8 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -371,10 +371,16 @@ class FireSimLargeBoomCospikeConfig extends Config(
   new WithFireSimConfigTweaks++
   new chipyard.LargeBoomV3Config)
 
+class FireSimQuadRocketSbusRingNoCConfig extends Config(
+  new chipyard.config.WithNoTraceIO ++
+  new WithDefaultFireSimBridges ++
+  new WithFireSimConfigTweaks++
+  new chipyard.QuadRocketSbusRingNoCConfig)
+
 class FireSimLargeBoomSV39CospikeConfig extends Config(
   new firesim.firesim.WithCospikeBridge ++
   new WithDefaultFireSimBridges ++
   new WithDefaultMemModel ++
   new WithFireSimConfigTweaks++
   new chipyard.config.WithSV39 ++
-  new chipyard.LargeBoomV3Config)
+  new chipyard.LargeBoomV3Config)
\ No newline at end of file
diff --git a/generators/rocket-chip b/generators/rocket-chip
index c10ce93f..e79ecc10 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit c10ce93fd1a4187599ea926603e8ce10d04f77d7
+Subproject commit e79ecc100b5d20cc32ce426d0d7440bbfaf29e61