diff --git a/common.mk b/common.mk index 43615a92..87d4047c 100644 --- a/common.mk +++ b/common.mk @@ -3,22 +3,46 @@ ######################################################################################### SHELL=/bin/bash - ifndef RISCV $(error RISCV is unset. You must set RISCV yourself, or through the Chipyard auto-generated env file) else $(info Running with RISCV=$(RISCV)) endif +######################################################################################### +# specify user-interface variables +######################################################################################### +HELP_COMPILATION_VARIABLES += \ +" EXTRA_GENERATOR_REQS = requirements needed for the main generator" \ +" EXTRA_SIM_CFLAGS = CFLAGS for building simulators" \ +" EXTRA_SIM_CXXFLAGS = CXXFLAGS for building simulators" \ +" EXTRA_SIM_LDFLAGS = LDFLAGS for building simulators" \ +" EXTRA_SIM_SOURCES = simulation sources needed for simulator" \ +" EXTRA_SIM_REQS = requirements to build the simulator" + +EXTRA_GENERATOR_REQS ?= +EXTRA_SIM_CXXFLAGS ?= +EXTRA_SIM_CFLAGS ?= +EXTRA_SIM_LDFLAGS ?= +EXTRA_SIM_SOURCES ?= +EXTRA_SIM_REQS ?= + +#---------------------------------------------------------------------------- +HELP_SIMULATION_VARIABLES += \ +" EXTRA_SIM_FLAGS = runtime simulation flags (passed within +permissive)" + +EXTRA_SIM_FLAGS ?= + +#---------------------------------------------------------------------------- +HELP_COMMANDS += \ +" run-binary = run [./$(shell basename $(sim))] and log instructions to file" \ +" run-binary-fast = run [./$(shell basename $(sim))] and don't log instructions" \ +" run-binary-debug = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \ +" verilog = generate intermediate verilog files from chisel elaboration and firrtl passes" ######################################################################################### -# extra make variables/rules from subprojects -# -# EXTRA_GENERATOR_REQS - requirements needed for the main generator -# EXTRA_SIM_FLAGS - runtime simulation flags -# EXTRA_SIM_CC_FLAGS - cc flags for simulators -# EXTRA_SIM_SOURCES - simulation sources needed for simulator -# EXTRA_SIM_REQS - requirements to build the simulator +# include additional subproject make fragments +# see HELP_COMPILATION_VARIABLES ######################################################################################### include $(base_dir)/generators/ariane/ariane.mk include $(base_dir)/generators/tracegen/tracegen.mk @@ -55,7 +79,6 @@ $(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@ touch $@ - ######################################################################################### # Bloop Project Definitions ######################################################################################### @@ -139,19 +162,19 @@ verilog: $(sim_vsrcs) ######################################################################################### # helper rules to run simulations ######################################################################################### -.PHONY: run-binary run-binary-fast run-binary-debug run-fast +.PHONY: run-binary run-binary-fast +.PHONY: run-binary-debug +.PHONY: run-fast + +# run normal binary with hardware-logged insn dissassembly run-binary: $(output_dir) $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) -######################################################################################### -# helper rules to run simulator as fast as possible -######################################################################################### +# run simulator as fast as possible (no insn disassembly) run-binary-fast: $(output_dir) $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 14ebae59..46b3a267 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -25,7 +25,10 @@ sim_prefix = simv sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug -include $(base_dir)/vcs.mk +PERMISSIVE_ON=+permissive +PERMISSIVE_OFF=+permissive-off + +WAVEFORM_FLAG=+vcdplusfile=$(sim_out_name).vpd .PHONY: default debug default: $(sim) @@ -36,22 +39,97 @@ debug: $(sim_debug) ######################################################################################### include $(base_dir)/common.mk +######################################################################################### +# verilator-specific user-interface variables and commands +######################################################################################### +HELP_COMPILATION_VARIABLES += +HELP_COMMANDS += \ +" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ +" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ +" clean = remove all debug/non-debug simulators and intermediate files" \ +" clean-sim = removes non-debug simulator and verilator-generated files" \ +" clean-sim-debug = removes debug simulator and verilator-generated files" + ######################################################################################### # vcs binary and arguments ######################################################################################### VCS = vcs -full64 -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(EXTRA_SIM_SOURCES) +PREPROC_DEFINES = \ + +define+VCS \ + +define+CLOCK_PERIOD=1.0 \ + +define+PRINTF_COND=$(TB).printf_cond \ + +define+STOP_COND=!$(TB).reset \ + +define+RANDOMIZE_MEM_INIT \ + +define+RANDOMIZE_REG_INIT \ + +define+RANDOMIZE_GARBAGE_ASSIGN \ + +define+RANDOMIZE_INVALID_ASSIGN + +VCS_NONCC_OPTS = \ + -notice \ + -line \ + +lint=all,noVCDE,noONGS,noUI \ + -timescale=1ns/1ps \ + -quiet \ + -q \ + +rad \ + +vcs+lic+wait \ + +vc+list \ + -error=noZMMCM \ + -error=PCWM-L \ + -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ + +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ + +incdir+$(build_dir) \ + $(PREPROC_DEFINES) \ + -f $(sim_common_files) \ + $(sim_vsrcs) + +#---------------------------------------------------------------------------------------- +# gcc configuration/optimization +#---------------------------------------------------------------------------------------- +# -flto slows down compilation on small-memory and breaks on firesim-manager +CMODE := -O3 -fbranch-probabilities -march=native + +VCS_CXXFLAGS = \ + $(CXXFLAGS) \ + $(CMODE) \ + -I$(VCS_HOME)/include \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -std=c++11 \ + $(EXTRA_SIM_CXXFLAGS) + +VCS_LDFLAGS = \ + $(LDFLAGS) \ + $(CMODE) \ + -L$(RISCV)/lib \ + -Wl,-rpath,$(RISCV)/lib \ + -L$(sim_dir) \ + -L$(dramsim_dir) \ + -lfesvr \ + -ldramsim \ + $(EXTRA_SIM_LDFLAGS) + +VCS_CC_OPTS = \ + -CFLAGS "$(VCS_CXXFLAGS)" \ + -LDFLAGS "$(VCS_LDFLAGS)" + +#---------------------------------------------------------------------------------------- +# full vcs+gcc opts +#---------------------------------------------------------------------------------------- +VCS_OPTS = $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) ######################################################################################### # vcs simulator rules ######################################################################################### $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ + rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ + -debug_pp $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) - rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - +define+DEBUG + rm -rf csrc && $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ \ + +define+DEBUG \ + -debug_pp ######################################################################################### # create a vcs vpd rule @@ -60,9 +138,26 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) +$(output_dir)/none.vpd: $(sim_debug) + mkdir -p $(output_dir) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) + ######################################################################################### -# general cleanup rule +# general cleanup rules ######################################################################################### -.PHONY: clean +.PHONY: clean clean-sim clean-sim-debug clean: - rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h + rm -rf $(gen_dir) $(sim_prefix)-* + +clean-sim: + rm -rf csrc/ $(sim) ucli.key vc_hdrs.h + +clean-sim-debug: + rm -rf csrc/ $(sim_debug) ucli.key vc_hdrs.h + +######################################################################################### +# print help text +######################################################################################### +.PHONY: help +help: + @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 3d676efd..07ece1c5 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -22,7 +22,7 @@ include $(base_dir)/variables.mk sim_name = verilator ######################################################################################### -# vcs simulator types and rules +# verilator simulator types and rules ######################################################################################### sim_prefix = simulator sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) @@ -47,67 +47,141 @@ debug: $(sim_debug) include $(base_dir)/common.mk ######################################################################################### -# verilator binary and flags +# verilator-specific user-interface variables and commands +######################################################################################### +HELP_COMPILATION_VARIABLES += \ +" VERILATOR_PROFILE = 'none' if no verilator profiling (default)" \ +" 'all' if full verilator runtime profiling" \ +" 'threads' if runtime thread profiling only" \ +" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build" + +HELP_COMMANDS += \ +" default = compiles non-debug simulator [./$(shell basename $(sim))]" \ +" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \ +" clean = remove all debug/non-debug simulators and intermediate files" \ +" clean-sim = removes non-debug simulator and verilator-generated files" \ +" clean-sim-debug = removes debug simulator and verilator-generated files" + +######################################################################################### +# verilator/cxx binary and flags ######################################################################################### VERILATOR := verilator --cc --exe -CXXFLAGS := \ - $(CXXFLAGS) -O1 -std=c++11 \ - -I$(RISCV)/include \ - -I$(dramsim_dir) \ - -D__STDC_FORMAT_MACROS \ - $(EXTRA_SIM_CC_FLAGS) +#---------------------------------------------------------------------------------------- +# user configs +#---------------------------------------------------------------------------------------- +VERILATOR_PROFILE ?= none +RUNTIME_PROFILING_CFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),-g -pg,) +RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\ + --prof-threads --prof-cfuncs,\ + $(if $(filter $(VERILATOR_PROFILE),threads),\ + --prof-threads,)) -LDFLAGS := \ - $(LDFLAGS) \ - -L$(sim_dir) \ - -lpthread +VERILATOR_FST_MODE ?= 0 +TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\ + --trace,--trace-fst --trace-threads 1) +TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE) -VERILATOR_CC_OPTS = \ +#---------------------------------------------------------------------------------------- +# verilation configuration/optimization +#---------------------------------------------------------------------------------------- +# we initially had --noassert for performance, but several modules use +# assertions, including dramsim, so we enable --assert by default +VMODE := \ -O3 \ - -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \ - -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \ - -LDFLAGS "$(LDFLAGS)" \ - $(RISCV)/lib/libfesvr.a \ - $(dramsim_lib) + --x-assign fast \ + --x-initial fast \ + --assert \ + --output-split 10000 \ + --output-split-cfuncs 10000 -# default flags added for ariane -ARIANE_VERILATOR_FLAGS = \ +# default flags added for ariane (-Wno-fatal needed for -Wall to not cause +# a crash, since 1000s of warnings are generated) +VERILOG_IP_VERILATOR_FLAGS := \ --unroll-count 256 \ - -Werror-PINMISSING \ - -Werror-IMPLICIT \ -Wno-PINCONNECTEMPTY \ -Wno-ASSIGNDLY \ -Wno-DECLFILENAME \ -Wno-UNUSED \ -Wno-UNOPTFLAT \ -Wno-BLKANDNBLK \ - -Wno-style \ - -Wall + -Wno-fatal -# normal flags used for chipyard builds (that are incompatible with ariane) -CHIPYARD_VERILATOR_FLAGS = \ - --assert +# normal flags used for chipyard builds (that are incompatible with vlog ip aka ariane) +CHIPYARD_VERILATOR_FLAGS := + +# options dependent on whether ariane/NVDLA or chipyard is used +# NOTE: defer the evaluation of this until it is used! +PLATFORM_OPTS = $(shell \ + if grep -qiP "module\s+(Ariane|NVDLA)" $(build_dir)/*.*v; \ + then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \ + else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi) # Use --timescale to approximate timescale behavior of pre-4.034 TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }') -VERILATOR_NONCC_OPTS = \ - $(TIMESCALE_OPTS) \ - --top-module $(VLOG_MODEL) \ - --vpi \ - -Wno-fatal \ - $(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \ - --output-split 10000 \ - --output-split-cfuncs 100 \ - --max-num-width 1048576 \ - -f $(sim_common_files) \ - $(sim_vsrcs) -VERILATOR_DEFINES = \ +# see: https://github.com/ucb-bar/riscv-mini/issues/31 +MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }') + +PREPROC_DEFINES := \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ +define+STOP_COND=\$$c\(\"done_reset\"\) -VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) $(EXTRA_SIM_SOURCES) +VERILATOR_NONCC_OPTS = \ + $(RUNTIME_PROFILING_VFLAGS) \ + $(VMODE) \ + $(PLATFORM_OPTS) \ + $(TIMESCALE_OPTS) \ + $(MAX_WIDTH_OPTS) \ + $(PREPROC_DEFINES) \ + --top-module $(VLOG_MODEL) \ + --vpi \ + -f $(sim_common_files) \ + $(sim_vsrcs) + +#---------------------------------------------------------------------------------------- +# gcc configuration/optimization +#---------------------------------------------------------------------------------------- +# -flto slows down compilation on small-memory and breaks on firesim-manager +CMODE := -O3 -fbranch-probabilities -march=native + +VERILATOR_CXXFLAGS = \ + $(CXXFLAGS) \ + $(RUNTIME_PROFILING_CFLAGS) \ + $(TRACING_CFLAGS) \ + $(CMODE) \ + -std=c++11 \ + -D__STDC_FORMAT_MACROS \ + -DTEST_HARNESS=V$(VLOG_MODEL) \ + -DVERILATOR \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -I$(build_dir) \ + -include $(build_dir)/$(long_name).plusArgs \ + -include $(build_dir)/verilator.h \ + $(EXTRA_SIM_CXXFLAGS) + +VERILATOR_LDFLAGS = \ + $(LDFLAGS) \ + $(RUNTIME_PROFILING_CFLAGS) \ + $(CMODE) \ + -L$(RISCV)/lib \ + -Wl,-rpath,$(RISCV)/lib \ + -L$(sim_dir) \ + -L$(dramsim_dir) \ + -lfesvr \ + -lpthread \ + -ldramsim \ + $(EXTRA_SIM_LDFLAGS) + +VERILATOR_CC_OPTS = \ + -CFLAGS "$(VERILATOR_CXXFLAGS)" \ + -LDFLAGS "$(VERILATOR_LDFLAGS)" + +#---------------------------------------------------------------------------------------- +# full verilator+gcc opts +#---------------------------------------------------------------------------------------- +VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) ######################################################################################### # verilator build paths and file names @@ -127,13 +201,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk $(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir) mkdir -p $(model_dir) - $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" + $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir_debug) mkdir -p $(model_dir_debug) - $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" + $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ ######################################################################################### @@ -155,8 +229,21 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### -# general cleanup rule +# general cleanup rules ######################################################################################### -.PHONY: clean +.PHONY: clean clean-sim clean-sim-debug clean: rm -rf $(gen_dir) $(sim_prefix)-* + +clean-sim: + rm -rf $(model_dir) $(sim) + +clean-sim-debug: + rm -rf $(model_dir_debug) $(sim_debug) + +######################################################################################### +# print help text +######################################################################################### +.PHONY: help +help: + @for line in $(HELP_LINES); do echo "$$line"; done diff --git a/tools/dromajo/dromajo.mk b/tools/dromajo/dromajo.mk index 067faa2f..4ac17764 100644 --- a/tools/dromajo/dromajo.mk +++ b/tools/dromajo/dromajo.mk @@ -49,7 +49,8 @@ ifdef ENABLE_DROMAJO EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS) # CC flags needed for all simulations -EXTRA_SIM_CC_FLAGS += -I$(DROMAJO_DIR) +EXTRA_SIM_CFLAGS += -I$(DROMAJO_DIR) +EXTRA_SIM_CXXFLAGS += -I$(DROMAJO_DIR) # sourced needed for simulation EXTRA_SIM_SOURCES += $(DROMAJO_LIB) diff --git a/variables.mk b/variables.mk index d7eccb49..e41648d4 100644 --- a/variables.mk +++ b/variables.mk @@ -1,23 +1,45 @@ ######################################################################################### # makefile variables shared across multiple makefiles +# - to use the help text, your Makefile should have a 'help' target that just +# prints all the HELP_LINES ######################################################################################### +HELP_COMPILATION_VARIABLES = +HELP_PROJECT_VARIABLES = \ +" SUB_PROJECT = use the specific subproject default variables [$(SUB_PROJECT)]" \ +" SBT_PROJECT = the SBT project that you should find the classes/packages in [$(SBT_PROJECT)]" \ +" MODEL = the top level module of the project in Chisel (normally the harness) [$(MODEL)]" \ +" VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) [$(VLOG_MODEL)]" \ +" MODEL_PACKAGE = the scala package to find the MODEL in [$(MODEL_PACKAGE)]" \ +" CONFIG = the configuration class to give the parameters for the project [$(CONFIG)]" \ +" CONFIG_PACKAGE = the scala package to find the CONFIG class [$(CONFIG_PACKAGE)]" \ +" GENERATOR_PACKAGE = the scala package to find the Generator class in [$(GENERATOR_PACKAGE)]" \ +" TB = wrapper over the TestHarness needed to simulate in a verilog simulator [$(TB)]" \ +" TOP = top level module of the project (normally the module instantiated by the harness) [$(TOP)]" -######################################################################################### -# variables to invoke the generator -# descriptions: -# SBT_PROJECT = the SBT project that you should find the classes/packages in -# MODEL = the top level module of the project in Chisel (normally the harness) -# VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) -# MODEL_PACKAGE = the scala package to find the MODEL in -# CONFIG = the configuration class to give the parameters for the project -# CONFIG_PACKAGE = the scala package to find the CONFIG class -# GENERATOR_PACKAGE = the scala package to find the Generator class in -# TB = wrapper over the TestHarness needed to simulate in a verilog simulator -# TOP = top level module of the project (normally the module instantiated by the harness) -# -# project specific: -# SUB_PROJECT = use the specific subproject default variables -######################################################################################### +HELP_SIMULATION_VARIABLES = \ +" BINARY = riscv binary that the simulator will run" \ +" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" + +HELP_COMMANDS = \ +" help = display this help" + +HELP_LINES = "" \ + " design specifier variables:" \ + " ---------------------------" \ + $(HELP_PROJECT_VARIABLES) \ + "" \ + " compilation variables:" \ + " ----------------------" \ + $(HELP_COMPILATION_VARIABLES) \ + "" \ + " simulation variables:" \ + " ---------------------" \ + $(HELP_SIMULATION_VARIABLES) \ + "" \ + " some useful general commands:" \ + " -----------------" \ + $(HELP_COMMANDS) \ + "" ######################################################################################### # subproject overrides @@ -140,15 +162,15 @@ override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP # 1) the sed removes a leading {file:} that sometimes needs to be # provided to SBT when a project but not for bloop. # 2) Generally, one could could pass '--' to indicate all remaining arguments are -# destined for the scala Main, however a bug in Bloop's argument parsing causes the +# destined for the scala Main, however a bug in Bloop's argument parsing causes the # --nailgun-port argument to be lost in this case. Workaround this by prefixing # every main-destined argument with "--args" define run_scala_main - cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) + cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3) endef else define run_scala_main - cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" + cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)" endef endif