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Merge remote-tracking branch 'origin/main' into clusters

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This commit is contained in:
Jerry Zhao
2023-12-16 17:00:34 -08:00
parent 6d60ad6c40 a181790649
commit b02621db35
18 changed files with 74 additions and 43 deletions
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2
fpga/src/main/scala/arty/Configs.scala
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@@ -27,6 +27,8 @@ class WithArtyTweaks extends Config(
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.config.WithDTSTimebase(32000) ++
new chipyard.config.WithSystemBusFrequency(32) ++
new chipyard.config.WithFrontBusFrequency(32) ++
new chipyard.config.WithControlBusFrequency(32) ++
new chipyard.config.WithPeripheryBusFrequency(32) ++
new chipyard.config.WithControlBusFrequency(32) ++
new testchipip.WithNoSerialTL

9
fpga/src/main/scala/vc707/Configs.scala
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@@ -35,7 +35,7 @@ class WithSystemModifications extends Config((site, here, up) => {
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin")
}
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size (note the size)
case SerialTLKey => None // remove serialized tl port
case SerialTLKey => Nil // remove serialized tl port
})
class WithVC707Tweaks extends Config (
@@ -46,6 +46,7 @@ class WithVC707Tweaks extends Config (
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new WithFPGAFrequency(50) ++ // default 50MHz freq
@@ -75,9 +76,11 @@ class BoomVC707Config extends Config (
)
class WithFPGAFrequency(fMHz: Double) extends Config (
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++
new chipyard.config.WithMemoryBusFrequency(fMHz) ++
new chipyard.config.WithSystemBusFrequency(fMHz) ++
new chipyard.config.WithControlBusFrequency(fMHz) ++
new chipyard.config.WithMemoryBusFrequency(fMHz)
new chipyard.config.WithFrontBusFrequency(fMHz)
)
class WithFPGAFreq25MHz extends WithFPGAFrequency(25)

4
fpga/src/main/scala/vcu118/Configs.scala
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@@ -36,7 +36,7 @@ class WithSystemModifications extends Config((site, here, up) => {
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
}
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size
case SerialTLKey => None // remove serialized tl port
case SerialTLKey => Nil // remove serialized tl port
})
// DOC include start: AbstractVCU118 and Rocket
@@ -46,6 +46,7 @@ class WithVCU118Tweaks extends Config(
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithMemoryBusFrequency(100) ++
new chipyard.config.WithSystemBusFrequency(100) ++
new chipyard.config.WithControlBusFrequency(100) ++
new chipyard.config.WithPeripheryBusFrequency(100) ++
new chipyard.config.WithControlBusFrequency(100) ++
new WithFPGAFrequency(100) ++ // default 100MHz freq
@@ -79,6 +80,7 @@ class WithFPGAFrequency(fMHz: Double) extends Config(
new chipyard.config.WithSystemBusFrequency(fMHz) ++
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++
new chipyard.config.WithControlBusFrequency(fMHz) ++
new chipyard.config.WithFrontBusFrequency(fMHz) ++
new chipyard.config.WithMemoryBusFrequency(fMHz)
)