diff --git a/common.mk b/common.mk
index cc2469a7..fe0cb023 100644
--- a/common.mk
+++ b/common.mk
@@ -33,45 +33,45 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala)
 #########################################################################################
 # create simulation args file rule
 #########################################################################################
-$(sim_dotf): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR)
+$(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR)
 	cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
 
 #########################################################################################
 # create firrtl file rule and variables
 #########################################################################################
-$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
+$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_files)
 	mkdir -p $(build_dir)
 	cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)"
 
 #########################################################################################
 # create verilog files rules and variables
 #########################################################################################
-REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
+REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF)
 HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF)
 
-$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
-	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
-	cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
+$(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
+	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(TOP_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
+	grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_top_blackboxes)
 
 # note: this depends on sim_top_blackboxes to avoid race condition where firrtl_black_box_resource_files.f is created at the same time
 $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
 	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)"
-	cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_harness_blackboxes)
+	grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
 MACROCOMPILER_MODE ?= --mode synflops
-$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF)
-	cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)"
+$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR): $(TOP_SMEMS_CONF)
+	cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)"
 
 HARNESS_MACROCOMPILER_MODE = --mode synflops
 $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF)
 	cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)"
 
 ########################################################################################
-# remove duplicate/*.h files in blackbox/simfiles
+# remove duplicate files in blackbox/simfiles
 ########################################################################################
-$(sim_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_dotf)
-	awk '{print $1;}' $^ | sort -u | grep -v ".*\.h" > $@
+$(sim_common_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_files)
+	awk '{print $1;}' $^ | sort -u > $@
 
 #########################################################################################
 # helper rule to just make verilog files
diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile
index 8f0ebbe0..fa05531f 100644
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -61,7 +61,7 @@ VCS_NONCC_OPTS = \
 	+v2k \
 	+vcs+lic+wait \
 	+vc+list \
-	-f $(sim_files) \
+	-f $(sim_common_files) \
 	-sverilog \
 	+incdir+$(build_dir) \
 	+define+CLOCK_PERIOD=1.0 \
@@ -79,11 +79,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS)
 #########################################################################################
 # vcs simulator rules
 #########################################################################################
-$(sim): $(sim_vsrcs) $(sim_files)
+$(sim): $(sim_vsrcs) $(sim_common_files)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	-debug_pp
 
-$(sim_debug) : $(sim_vsrcs) $(sim_files)
+$(sim_debug) : $(sim_vsrcs) $(sim_common_files)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	+define+DEBUG -debug_pp
 
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index 2dfd43ba..3edbc953 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -56,20 +56,29 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
 # build makefile fragment that builds the verilator sim rules
 #########################################################################################
 LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
+SHARED_FLAGS := \
+	$(sim_vsrcs) \
+	-f $(sim_common_files) \
+	-LDFLAGS "$(LDFLAGS)"
 
-$(model_mk): $(sim_vsrcs) $(sim_files) $(INSTALLED_VERILATOR)
+$(model_mk): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name)
-	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-	-o $(sim) $(sim_vsrcs) -f $(sim_files) -LDFLAGS "$(LDFLAGS)" \
+	$(VERILATOR) $(VERILATOR_FLAGS) \
+	-Mdir $(build_dir)/$(long_name) \
+	-o $(sim) \
+	$(SHARED_FLAGS) \
 	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
 	touch $@
 
-$(model_mk_debug): $(sim_vsrcs) $(sim_files) $(INSTALLED_VERILATOR)
+$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name).debug
-	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-	-o $(sim_debug) $(sim_vsrcs) -f $(sim_files) -LDFLAGS "$(LDFLAGS)" \
+	$(VERILATOR) $(VERILATOR_FLAGS) \
+	-Mdir $(build_dir)/$(long_name).debug \
+	--trace \
+	-o $(sim_debug)  \
+	$(SHARED_FLAGS) \
 	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
 	touch $@
 
diff --git a/sims/verilator/verilator.mk b/sims/verilator/verilator.mk
index 80abd869..382715ca 100644
--- a/sims/verilator/verilator.mk
+++ b/sims/verilator/verilator.mk
@@ -6,7 +6,7 @@
 # verilator version, binary, and path
 #########################################################################################
 VERILATOR_VERSION      = 4.016
-VERILATOR_INSTALL_DIR ?= verilator
+VERILATOR_INSTALL_DIR ?= verilator_install
 VERILATOR_SRCDIR       = $(VERILATOR_INSTALL_DIR)/src/verilator-$(VERILATOR_VERSION)
 INSTALLED_VERILATOR    = $(abspath $(VERILATOR_INSTALL_DIR)/install/bin/verilator)
 
@@ -45,7 +45,8 @@ VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
 CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
 VERILATOR_FLAGS := --top-module $(VLOG_MODEL) \
 	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
-	+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
+	+define+STOP_COND=\$$c\(\"done_reset\"\) \
+	--assert \
 	--output-split 20000 \
 	-Wno-STMTDLY --x-assign unique \
 	-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR"
diff --git a/variables.mk b/variables.mk
index 06e08136..f0bdf634 100644
--- a/variables.mk
+++ b/variables.mk
@@ -108,24 +108,28 @@ ifeq ($(GENERATOR_PACKAGE),hwacha)
 	long_name=$(MODEL_PACKAGE).$(CONFIG)
 endif
 
-FIRRTL_FILE        ?= $(build_dir)/$(long_name).fir
-ANNO_FILE          ?= $(build_dir)/$(long_name).anno.json
-VERILOG_FILE       ?= $(build_dir)/$(long_name).top.v
-TOP_FIR            ?= $(build_dir)/$(long_name).top.fir
-TOP_ANNO           ?= $(build_dir)/$(long_name).top.anno.json
+FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
+ANNO_FILE   ?= $(build_dir)/$(long_name).anno.json
+
+TOP_FILE       ?= $(build_dir)/$(long_name).top.v
+TOP_FIR        ?= $(build_dir)/$(long_name).top.fir
+TOP_ANNO       ?= $(build_dir)/$(long_name).top.anno.json
+TOP_SMEMS_FILE ?= $(build_dir)/$(long_name).top.mems.v
+TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf
+TOP_SMEMS_FIR  ?= $(build_dir)/$(long_name).top.mems.fir
+
 HARNESS_FILE       ?= $(build_dir)/$(long_name).harness.v
 HARNESS_FIR        ?= $(build_dir)/$(long_name).harness.fir
 HARNESS_ANNO       ?= $(build_dir)/$(long_name).harness.anno.json
 HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v
 HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf
 HARNESS_SMEMS_FIR  ?= $(build_dir)/$(long_name).harness.mems.fir
-SMEMS_FILE         ?= $(build_dir)/$(long_name).mems.v
-SMEMS_CONF         ?= $(build_dir)/$(long_name).mems.conf
-SMEMS_FIR          ?= $(build_dir)/$(long_name).mems.fir
-sim_files              ?= $(build_dir)/sim_files.common.f
-sim_dotf               ?= $(build_dir)/sim_files.f
-sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
-sim_top_blackboxes     ?= $(build_dir)/firrtl_black_box_resource_files.top.f
+
+sim_files                  ?= $(build_dir)/sim_files.f
+sim_files                  ?= $(build_dir)/sim_files.f
+sim_top_blackboxes         ?= $(build_dir)/firrtl_black_box_resource_files.top.f
+sim_harness_blackboxes     ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
+sim_common_files           ?= $(build_dir)/sim_files.common.f
 
 #########################################################################################
 # java arguments used in sbt
@@ -168,9 +172,9 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
 # sources needed to run simulators
 #########################################################################################
 sim_vsrcs = \
-	$(VERILOG_FILE) \
+	$(TOP_FILE) \
 	$(HARNESS_FILE) \
-	$(SMEMS_FILE) \
+	$(TOP_SMEMS_FILE) \
 	$(HARNESS_SMEMS_FILE)
 
 #########################################################################################