diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
index 11cf0260..bc62bcf9 100644
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -11,6 +11,8 @@ import freechips.rocketchip.tile._
 
 import sifive.blocks.devices.uart._
 
+import testchipip.{SerialTLKey}
+
 import chipyard.{BuildSystem}
 
 class WithDefaultPeripherals extends Config((site, here, up) => {
@@ -22,29 +24,20 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
     idcodePartNum = 0x000,
     idcodeManufId = 0x489,
     debugIdleCycles = 5)
+  case SerialTLKey => None // remove serialized tl port
 })
 
-class TinyRocketArtyConfig extends Config(
+class WithArtyTweaks extends Config(
   new WithArtyJTAGHarnessBinder ++
   new WithArtyUARTHarnessBinder ++
   new WithArtyResetHarnessBinder ++
-  new chipyard.iobinders.WithDebugIOCells ++
-  new chipyard.iobinders.WithUARTIOCells ++
   new WithResetPassthrough ++
   new WithDefaultPeripherals ++
-  new chipyard.config.WithNoSubsystemDrivenClocks ++
-  new chipyard.config.WithPeripheryBusFrequencyAsDefault ++
-  new chipyard.config.WithBootROM ++
-  new chipyard.config.WithL2TLBs(1024) ++
-  new freechips.rocketchip.subsystem.With1TinyCore ++
-  new freechips.rocketchip.subsystem.WithNBanks(0) ++
-  new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$
+  new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory
   new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
-  new freechips.rocketchip.subsystem.WithJtagDTM ++
-  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
-  new freechips.rocketchip.subsystem.WithNoSlavePort ++
-  new freechips.rocketchip.subsystem.WithInclusiveCache ++
-  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
-  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
-  new freechips.rocketchip.system.BaseConfig)
+  new freechips.rocketchip.subsystem.WithIncoherentBusTopology)
+
+class TinyRocketArtyConfig extends Config(
+  new WithArtyTweaks ++
+  new chipyard.TinyRocketConfig)
diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index 408d2b7d..464d054a 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -59,7 +59,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
   }
 })
 
-class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({
+class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({
   (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => {
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
       IOBUF(th.uart_txd_in,  ports.head.txd)
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index d413cc12..626700a5 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -10,6 +10,10 @@ class RocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
 
+class TinyRocketConfig extends Config(
+  new freechips.rocketchip.subsystem.With1TinyCore ++            // single tiny rocket-core
+  new chipyard.config.AbstractConfig)
+
 class HwachaRocketConfig extends Config(
   new chipyard.config.WithHwachaTest ++
   new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator