From b1b047bdc2cf6045823743db53b6b42588ad8378 Mon Sep 17 00:00:00 2001 From: John Wright Date: Sun, 14 Nov 2021 18:31:26 -0800 Subject: [PATCH] Fix WithAXI4MMIOPunchthrough IO binder to use the SBUS instead of MBUS. Also adds a config and test --- .circleci/defaults.sh | 3 ++- generators/chipyard/src/main/scala/IOBinders.scala | 2 +- .../chipyard/src/main/scala/config/RocketConfigs.scala | 6 ++++++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 2d49d92a..bfb63a33 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -49,7 +49,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket" +grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad" grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif" grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -80,6 +80,7 @@ mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig" mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig" +mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 65c8754f..1903ddc3 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -297,7 +297,7 @@ class WithAXI4MMIOPunchthrough extends OverrideLazyIOBinder({ (system: CanHaveMasterAXI4MMIOPort) => { implicit val p: Parameters = GetSystemParameters(system) val clockSinkNode = p(ExtBus).map(_ => ClockSinkNode(Seq(ClockSinkParameters()))) - clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(MBUS).fixedClockNode) + clockSinkNode.map(_ := system.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(SBUS).fixedClockNode) def clockBundle = clockSinkNode.get.in.head._1 InModuleBody { diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 96257838..43bb2fb2 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -143,6 +143,12 @@ class ScratchpadOnlyRocketConfig extends Config( new chipyard.config.AbstractConfig) // DOC include end: l1scratchpadrocket +class MMIOScratchpadOnlyRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port + new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port + new ScratchpadOnlyRocketConfig +) + class L1ScratchpadRocketConfig extends Config( new chipyard.config.WithRocketICacheScratchpad ++ // use rocket ICache scratchpad new chipyard.config.WithRocketDCacheScratchpad ++ // use rocket DCache scratchpad