From b1b230ba01fca4ae144cd9e7d8ed1194a2ec4ef3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 10 Jan 2021 23:38:11 -0800 Subject: [PATCH] Fix ICache SPAD base addr to avoid conflicts with default SerialTL mem --- generators/chipyard/src/main/scala/ConfigFragments.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index c5c85e47..d25b4aac 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -141,7 +141,7 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => { class WithRocketICacheScratchpad extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey, site) map { r => - r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x100000 + r.hartId * 0x10000)))) + r.copy(icache = r.icache.map(_.copy(itimAddr = Some(0x300000 + r.hartId * 0x10000)))) } })