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Rocket Chip Stage/Phase Bump (#503)

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[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules
This commit is contained in:
David Biancolin
2020-04-08 14:47:57 -07:00
parent 003bc4afcf
commit b303cf6e81
38 changed files with 406 additions and 256 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
.circleci/config.yml
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@@ -338,6 +338,7 @@ jobs:
steps:
- run-tests:
project-key: "chipyard-ariane"
timeout: "30m"
# Order and dependencies of jobs to run
workflows:

1
.circleci/defaults.sh
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@@ -47,7 +47,6 @@ mapping["chipyard-rocket"]="SUB_PROJECT=chipyard"
mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig"
mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig"
mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig"
mapping["rocketchip"]="SUB_PROJECT=rocketchip"
mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig"
mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig"
mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig"

1
build.sbt
View File

@@ -166,6 +166,7 @@ lazy val gemmini = (project in file("generators/gemmini"))
lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
.dependsOn(chisel_testers, chipyard)
.settings(commonSettings)
.settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0"))
lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/"))
.settings(commonSettings)

6
common.mk
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@@ -58,7 +58,11 @@ $(FIRRTL_FILE) $(ANNO_FILE): generator_temp
# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile
generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS)
mkdir -p $(build_dir)
cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)"
cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator \
--target-dir $(build_dir) \
--name $(long_name) \
--top-module $(MODEL_PACKAGE).$(MODEL) \
--legacy-configs $(CONFIG_PACKAGE).$(CONFIG)"
.PHONY: firrtl
firrtl: $(FIRRTL_FILE)

2
generators/ariane

Submodule generators/ariane updated: e02436d2aa...621201b1d5

2
generators/boom

Submodule generators/boom updated: a26504f34d...90911dde1b

95
generators/chipyard/src/main/scala/ChipTop.scala
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@@ -12,7 +12,42 @@ import chipyard.iobinders.{IOBinders, TestHarnessFunction, IOBinderTuple}
import barstools.iocell.chisel._
case object BuildSystem extends Field[Parameters => RawModule]((p: Parameters) => Module(LazyModule(new DigitalTop()(p)).suggestName("system").module))
case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => LazyModule(new DigitalTop()(p)))
/**
* Chipyard provides three baseline, top-level reset schemes, set using the
* [[GlobalResetSchemeKey]] in a Parameters instance. These are:
*
* 1) Synchronous: The input coming to the chip is synchronous to the provided
* clocks and will be used without modification as a synchronous reset.
* This is safe only for use in FireSim and SW simulation.
*
* 2) Asynchronous: The input reset is asynchronous to the input clock, but it
* is caught and synchronized to that clock before it is dissemenated.
* Thus, downsteam modules will be emitted with synchronously reset state
* elements.
*
* 3) Asynchronous Full: The input reset is asynchronous to the input clock,
* and is used globally as an async reset. Downstream modules will be emitted
* with asynchronously reset state elements.
*
*/
sealed trait GlobalResetScheme {
def pinIsAsync: Boolean
}
sealed trait HasAsyncInput { self: GlobalResetScheme =>
def pinIsAsync = true
}
sealed trait HasSyncInput { self: GlobalResetScheme =>
def pinIsAsync = false
}
case object GlobalResetSynchronous extends GlobalResetScheme with HasSyncInput
case object GlobalResetAsynchronous extends GlobalResetScheme with HasAsyncInput
case object GlobalResetAsynchronousFull extends GlobalResetScheme with HasAsyncInput
case object GlobalResetSchemeKey extends Field[GlobalResetScheme](GlobalResetSynchronous)
/**
* The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter,
@@ -26,16 +61,21 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with
// A list of functions to call in the test harness
val harnessFunctions = ArrayBuffer.empty[TestHarnessFunction]
// The system clock
// These are given so that IOCell can use DataMirror and generate ports with
// the right flow (Input/Output)
val systemClock = Wire(Input(Clock()))
// The system reset (synchronous to clock)
val systemReset = Wire(Input(Bool()))
val systemReset = Wire(Input(Reset()))
// The system module specified by BuildSystem
val system = withClockAndReset(systemClock, systemReset) { p(BuildSystem)(p) }
val lSystem = p(BuildSystem)(p).suggestName("system")
val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) }
// Call all of the IOBinders and provide them with a default clock and reset
withClockAndReset(systemClock, systemReset) {
val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.map(_(system)).flatten.unzip3
// Call each IOBinder on both the lazyModule instance and the module
// instance. Generally, an IOBinder PF should only be defined on one, so
// this should not lead to two invocations.
val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3
// We ignore _ports for now...
iocells ++= _iocells.flatten
harnessFunctions ++= _harnessFunctions.flatten
@@ -45,13 +85,22 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with
/**
* A simple clock and reset implementation that punches out clock and reset ports with the same
* names as the implicit clock and reset for standard Module classes. Reset is synchronous to
* clock, which may not be a good idea to use for tapeouts.
* names as the implicit clock and reset for standard Module classes. Three basic reset schemes
* are provided. See [[GlobalResetScheme]].
*/
trait HasChipTopSimpleClockAndReset { this: BaseChipTop =>
val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock"))
val (reset, systemResetIO) = IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"))
val (reset, systemResetIO) = p(GlobalResetSchemeKey) match {
case GlobalResetSynchronous =>
IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"))
case GlobalResetAsynchronousFull =>
IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"), abstractResetAsAsync = true)
case GlobalResetAsynchronous =>
val asyncResetCore = Wire(Input(AsyncReset()))
systemReset := ResetCatchAndSync(systemClock, asyncResetCore.asBool)
IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_reset"), abstractResetAsAsync = true)
}
iocells ++= systemClockIO
iocells ++= systemResetIO
@@ -68,35 +117,5 @@ trait HasChipTopSimpleClockAndReset { this: BaseChipTop =>
}
/**
* Variant of HasChipTopSimpleClockAndReset that adds a reset synchronizer so that the top-level reset
* can be asynchronous with clock, which is useful for tapeout configs.
*/
trait HasChipTopSimpleClockAndCaughtReset { this: BaseChipTop =>
val asyncResetCore = Wire(Input(Bool()))
systemReset := ResetCatchAndSync(systemClock, asyncResetCore)
val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock"))
val (areset, asyncResetIO) = IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_areset"))
iocells ++= systemClockIO
iocells ++= asyncResetIO
// Add a TestHarnessFunction that connects clock and areset
harnessFunctions += { (th: TestHarness) => {
// Connect clock; it's not done implicitly with RawModule
clock := th.clock
// Connect reset; it's not done implicitly with RawModule
// Note that we need to use dutReset, not harnessReset
areset := th.dutReset
Nil
} }
}
class ChipTop()(implicit p: Parameters) extends BaseChipTop()(p)
with HasChipTopSimpleClockAndReset
class ChipTopCaughtReset()(implicit p: Parameters) extends BaseChipTop()(p)
with HasChipTopSimpleClockAndCaughtReset

14
generators/chipyard/src/main/scala/ConfigFragments.scala
View File

@@ -21,7 +21,7 @@ import hwacha.{Hwacha}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._
import chipyard.{BuildTop, BuildSystem, ChipTopCaughtReset}
import chipyard.{BuildTop, BuildSystem}
/**
* TODO: Why do we need this?
@@ -66,7 +66,7 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
})
class WithTracegenSystem extends Config((site, here, up) => {
case BuildSystem => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module)
case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p))
})
@@ -150,13 +150,3 @@ class WithControlCore extends Config((site, here, up) => {
)
case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
})
/**
* Config fragment to use ChipTopCaughtReset as the top module, which adds a reset synchronizer to
* the top-level reset, allowing it to be asynchronous with the clock.
* NOTE: You must remember to set TOP=WithChipTopCaughtReset when building with this config
*/
class WithChipTopCaughtReset extends Config((site, here, up) => {
case BuildTop => (p: Parameters) => Module(new ChipTopCaughtReset()(p).suggestName("top"))
})

40
generators/chipyard/src/main/scala/Generator.scala
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@@ -1,40 +1,6 @@
package chipyard
import scala.util.Try
import firrtl.options.{StageMain}
import chipyard.stage.ChipyardStage
import chisel3._
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.util.{GeneratorApp}
import freechips.rocketchip.system.{TestGeneration}
object Generator extends GeneratorApp {
// add unique test suites
override def addTestSuites {
implicit val p: Parameters = params
TestSuiteHelper.addRocketTestSuites
TestSuiteHelper.addBoomTestSuites
TestSuiteHelper.addArianeTestSuites
// if hwacha parameter exists then generate its tests
// TODO: find a more elegant way to do this. either through
// trying to disambiguate BuildRoCC, having a AccelParamsKey,
// or having the Accelerator/Tile add its own tests
import hwacha.HwachaTestSuites._
if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
TestGeneration.addSuites(rv64uv.map(_("p")))
TestGeneration.addSuites(rv64uv.map(_("vp")))
TestGeneration.addSuite(rv64sv("p"))
TestGeneration.addSuite(hwachaBmarks)
}
}
// specify the name that the generator outputs files as
override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
// generate files
generateFirrtl
generateAnno
generateTestSuiteMakefrags
generateArtefacts
}
object Generator extends StageMain(new ChipyardStage)

64
generators/chipyard/src/main/scala/IOBinders.scala
View File

@@ -8,6 +8,7 @@ import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.util._
import sifive.blocks.devices.gpio._
@@ -117,17 +118,28 @@ object AddIOCells {
/**
* Add IO cells to a debug module and name the IO ports.
* @param gpios A PSDIO bundle
* @param resetctrlOpt An optional ResetCtrlIO bundle
* @param debugOpt An optional DebugIO bundle
* @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references)
*/
def debug(psd: PSDIO, debugOpt: Option[DebugIO]): (PSDIO, Option[DebugIO], Seq[IOCell]) = {
val (psdPort, psdIOs) = IOCell.generateIOFromSignal(psd, Some("iocell_psd"))
val optTuple = debugOpt.map(d => IOCell.generateIOFromSignal(d, Some("iocell_debug")))
val debugPortOpt: Option[DebugIO] = optTuple.map(_._1)
val debugIOs: Seq[IOCell] = optTuple.map(_._2).toSeq.flatten
def debug(psd: PSDIO, resetctrlOpt: Option[ResetCtrlIO], debugOpt: Option[DebugIO])(implicit p: Parameters):
(PSDIO, Option[ResetCtrlIO], Option[DebugIO], Seq[IOCell]) = {
val (psdPort, psdIOs) = IOCell.generateIOFromSignal(
psd, Some("iocell_psd"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
val debugTuple = debugOpt.map(d =>
IOCell.generateIOFromSignal(d, Some("iocell_debug"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync))
val debugPortOpt: Option[DebugIO] = debugTuple.map(_._1)
val debugIOs: Seq[IOCell] = debugTuple.map(_._2).toSeq.flatten
debugPortOpt.foreach(_.suggestName("debug"))
val resetctrlTuple = resetctrlOpt.map(d =>
IOCell.generateIOFromSignal(d, Some("iocell_resetctrl"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync))
val resetctrlPortOpt: Option[ResetCtrlIO] = resetctrlTuple.map(_._1)
val resetctrlIOs: Seq[IOCell] = resetctrlTuple.map(_._2).toSeq.flatten
resetctrlPortOpt.foreach(_.suggestName("resetctrl"))
psdPort.suggestName("psd")
(psdPort, debugPortOpt, psdIOs ++ debugIOs)
(psdPort, resetctrlPortOpt, debugPortOpt, psdIOs ++ debugIOs ++ resetctrlIOs)
}
/**
@@ -176,29 +188,32 @@ class WithSimNIC extends OverrideIOBinder({
(system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil
})
// Note: The parameters instance is accessible only through the BaseSubsystem
// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The
// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it
// accessible to the IOBinder
// DOC include start: WithSimAXIMem
class WithSimAXIMem extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPortModuleImp) => system.connectSimAXIMem(); Nil
(system: CanHaveMasterAXI4MemPort with BaseSubsystem) => SimAXIMem.connectMem(system)(system.p); Nil
})
// DOC include end: WithSimAXIMem
class WithBlackBoxSimMem extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPortModuleImp) => {
(system.mem_axi4 zip system.outer.memAXI4Node).foreach { case (io, node) =>
(system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
(system.mem_axi4 zip system.memAXI4Node.in).foreach { case (io, (_, edge)) =>
val memSize = system.p(ExtMem).get.master.size
val lineSize = system.p(CacheBlockBytes)
(io zip node.in).foreach { case (axi4, (_, edge)) =>
val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle))
mem.io.axi <> axi4
mem.io.clock := system.clock
mem.io.reset := system.reset
mem.io.axi <> io
mem.io.clock := system.module.clock
mem.io.reset := system.module.reset
}
}; Nil
Nil
}
})
class WithSimAXIMMIO extends OverrideIOBinder({
(system: CanHaveMasterAXI4MMIOPortModuleImp) => system.connectSimAXIMMIO(); Nil
(system: CanHaveMasterAXI4MMIOPort with BaseSubsystem) => SimAXIMem.connectMMIO(system)(system.p); Nil
})
class WithDontTouchPorts extends OverrideIOBinder({
@@ -215,7 +230,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({
})
class WithTieOffL2FBusAXI extends OverrideIOBinder({
(system: CanHaveSlaveAXI4PortModuleImp) => {
(system: CanHaveSlaveAXI4Port with BaseSubsystem) => {
system.l2_frontend_bus_axi4.foreach(axi => {
axi.tieoff()
experimental.DataMirror.directionOf(axi.ar.ready) match {
@@ -235,23 +250,28 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({
class WithTiedOffDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp) => {
val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug)
val (psdPort, resetctrlOpt, debugPortOpt, ioCells) =
AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p)
val harnessFn = (th: chipyard.TestHarness) => {
Debug.tieoffDebug(debugPortOpt, psdPort)
Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p)
// tieoffDebug doesn't actually tie everything off :/
debugPortOpt.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }))
debugPortOpt.foreach { d =>
d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
d.dmactiveAck := DontCare
}
Nil
}
Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn)))
Seq((Seq(psdPort) ++ resetctrlOpt ++ debugPortOpt.toSeq, Nil, Some(harnessFn)))
}
})
class WithSimDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp) => {
val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug)
val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) =
AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p)
val harnessFn = (th: chipyard.TestHarness) => {
val dtm_success = Wire(Bool())
Debug.connectDebug(debugPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p)
Debug.connectDebug(debugPortOpt, resetctrlPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p)
when (dtm_success) { th.success := true.B }
th.dutReset := th.harnessReset | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B)
Nil

16
generators/chipyard/src/main/scala/Subsystem.scala
View File

@@ -52,26 +52,20 @@ trait HasChipyardTiles extends HasTiles
// TODO: investigate why
val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map {
case (param, crossing) => {
val (tile, rocketLogicalTree) = param match {
val tile = param match {
case r: RocketTileParams => {
val t = LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
(t, t.rocketLogicalTree)
LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
}
case b: BoomTileParams => {
val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
(t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
}
case a: ArianeTileParams => {
val t = LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
(t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately
LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
}
}
connectMasterPortsToSBus(tile, crossing)
connectSlavePortsToCBus(tile, crossing)
def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocketLogicalTree.getOMInterruptTargets)
LogicalModuleTree.add(logicalTreeNode, rocketLogicalTree)
connectInterrupts(tile, debugOpt, clintOpt, plicOpt)
tile

3
generators/chipyard/src/main/scala/System.scala
View File

@@ -38,8 +38,5 @@ class System(implicit p: Parameters) extends Subsystem
class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer)
with HasRTCModuleImp
with HasExtInterruptsModuleImp
with CanHaveMasterAXI4MemPortModuleImp
with CanHaveMasterAXI4MMIOPortModuleImp
with CanHaveSlaveAXI4PortModuleImp
with HasPeripheryBootROMModuleImp
with DontTouch

5
generators/chipyard/src/main/scala/TestHarness.scala
View File

@@ -25,9 +25,8 @@ class TestHarness(implicit val p: Parameters) extends Module {
val dut = p(BuildTop)(p)
io.success := false.B
// dutReset can be overridden via a harnessFunction, but by default it is just reset
val dutReset = Wire(Bool())
dutReset := reset
// dutReset assignment can be overridden via a harnessFunction, but by default it is just reset
val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset)
dut.harnessFunctions.foreach(_(this))

83
generators/chipyard/src/main/scala/TestSuites.scala
View File

@@ -5,8 +5,7 @@ import scala.collection.mutable.{LinkedHashSet}
import freechips.rocketchip.subsystem.{RocketTilesKey}
import freechips.rocketchip.tile.{XLen}
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.util.{GeneratorApp}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
import boom.common.{BoomTilesKey}
import ariane.{ArianeTilesKey}
@@ -56,10 +55,13 @@ object RegressionTestSuites
/**
* Helper functions to add BOOM or Rocket tests
*/
object TestSuiteHelper
class TestSuiteHelper
{
import freechips.rocketchip.system.DefaultTestSuites._
import RegressionTestSuites._
val suites = collection.mutable.ListMap[String, RocketTestSuite]()
def addSuite(s: RocketTestSuite) { suites += (s.makeTargetName -> s) }
def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
/**
* Add BOOM tests (asm, bmark, regression)
@@ -72,33 +74,33 @@ object TestSuiteHelper
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
addSuites(env.map(rv32uf))
if (cfg.fLen >= 64) {
TestGeneration.addSuites(env.map(rv32ud))
addSuites(env.map(rv32ud))
}
} else if (cfg.fLen >= 64) {
TestGeneration.addSuites(env.map(rv64ud))
TestGeneration.addSuites(env.map(rv64uf))
TestGeneration.addSuite(rv32udBenchmarks)
addSuites(env.map(rv64ud))
addSuites(env.map(rv64uf))
addSuite(rv32udBenchmarks)
}
}
if (coreParams.useAtomics) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
} else {
TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
}
}
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
val (rvi, rvu) =
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites(rvu.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
addSuites(rvi.map(_("p")))
addSuites(rvu.map(_("p")))
addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
addSuite(benchmarks)
addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
}
@@ -113,31 +115,31 @@ object TestSuiteHelper
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
addSuites(env.map(rv32uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv32ud))
addSuites(env.map(rv32ud))
} else {
TestGeneration.addSuite(rv32udBenchmarks)
TestGeneration.addSuites(env.map(rv64uf))
addSuite(rv32udBenchmarks)
addSuites(env.map(rv64uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv64ud))
addSuites(env.map(rv64ud))
}
}
if (coreParams.useAtomics) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty)
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
else
TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
}
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
val (rvi, rvu) =
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
addSuites(rvi.map(_("p")))
addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
addSuite(benchmarks)
addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
}
@@ -152,32 +154,31 @@ object TestSuiteHelper
val env = if (vm) List("p","v") else List("p")
coreParams.fpu foreach { case cfg =>
if (xlen == 32) {
TestGeneration.addSuites(env.map(rv32uf))
addSuites(env.map(rv32uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv32ud))
addSuites(env.map(rv32ud))
} else {
TestGeneration.addSuite(rv32udBenchmarks)
TestGeneration.addSuites(env.map(rv64uf))
addSuite(rv32udBenchmarks)
addSuites(env.map(rv64uf))
if (cfg.fLen >= 64)
TestGeneration.addSuites(env.map(rv64ud))
addSuites(env.map(rv64ud))
}
}
if (coreParams.useAtomics) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty)
TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
else
TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
}
if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
val (rvi, rvu) =
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
else ((if (vm) rv32i else rv32pi), rv32u)
TestGeneration.addSuites(rvi.map(_("p")))
TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
TestGeneration.addSuite(benchmarks)
TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
addSuites(rvi.map(_("p")))
addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
addSuite(benchmarks)
addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
}
}

20
generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala Normal file
View File

@@ -0,0 +1,20 @@
// See LICENSE for license details.
// Based on Rocket Chip's stage implementation
package chipyard.stage
import freechips.rocketchip.stage.ConfigsAnnotation
import firrtl.options.{HasShellOptions, ShellOption}
/** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format */
private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions {
override val options = Seq(
new ShellOption[String](
longOption = "legacy-configs",
toAnnotationSeq = a => Seq(new ConfigsAnnotation(a.split("_"))),
helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).",
shortOption = Some("LC")
)
)
}

15
generators/chipyard/src/main/scala/stage/ChipyardCli.scala Normal file
View File

@@ -0,0 +1,15 @@
// See LICENSE for license details.
// Based on Rocket Chip's stage implementation
package chipyard.stage
import firrtl.options.Shell
trait ChipyardCli { this: Shell =>
parser.note("Chipyard Generator Options")
Seq(
UnderscoreDelimitedConfigsAnnotation
)
.foreach(_.addOptions(parser))
}

36
generators/chipyard/src/main/scala/stage/ChipyardStage.scala Normal file
View File

@@ -0,0 +1,36 @@
// See LICENSE for license details.
// Based on Rocket Chip's stage implementation
package chipyard.stage
import chisel3.stage.{ChiselCli, ChiselStage}
import firrtl.options.PhaseManager.PhaseDependency
import firrtl.options.{Phase, PreservesAll, Shell}
import firrtl.stage.FirrtlCli
import freechips.rocketchip.stage.RocketChipCli
import freechips.rocketchip.system.RocketChipStage
import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain}
import firrtl.options.phases.DeletedWrapper
class ChipyardStage extends ChiselStage with PreservesAll[Phase] {
override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli
override val targets: Seq[PhaseDependency] = Seq(
classOf[freechips.rocketchip.stage.phases.Checks],
classOf[freechips.rocketchip.stage.phases.TransformAnnotations],
classOf[freechips.rocketchip.stage.phases.PreElaboration],
classOf[chisel3.stage.phases.Checks],
classOf[chisel3.stage.phases.Elaborate],
classOf[freechips.rocketchip.stage.phases.GenerateROMs],
classOf[chisel3.stage.phases.AddImplicitOutputFile],
classOf[chisel3.stage.phases.AddImplicitOutputAnnotationFile],
classOf[chisel3.stage.phases.MaybeAspectPhase],
classOf[chisel3.stage.phases.Emitter],
classOf[chisel3.stage.phases.Convert],
classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
classOf[freechips.rocketchip.stage.phases.AddDefaultTests],
classOf[chipyard.stage.phases.AddDefaultTests],
classOf[chipyard.stage.phases.GenerateTestSuiteMakefrags],
classOf[freechips.rocketchip.stage.phases.GenerateArtefacts],
)
}

62
generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala Normal file
View File

@@ -0,0 +1,62 @@
// See LICENSE for license details.
// Based on Rocket Chip's stage implementation
package chipyard.stage.phases
import scala.util.Try
import scala.collection.mutable
import chipsalliance.rocketchip.config.Parameters
import chisel3.stage.phases.Elaborate
import firrtl.AnnotationSeq
import firrtl.annotations.{Annotation, NoTargetAnnotation}
import firrtl.options.{Phase, PreservesAll}
import firrtl.options.Viewer.view
import freechips.rocketchip.stage.RocketChipOptions
import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
import freechips.rocketchip.system.{RocketTestSuite, TestGeneration}
import freechips.rocketchip.util.HasRocketChipStageUtils
import chipyard.TestSuiteHelper
class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
// Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
// because the RocketTestSuiteAnnotation is not serializable (but is not marked as such).
override val prerequisites = Seq(
classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
classOf[freechips.rocketchip.stage.phases.AddDefaultTests])
override val dependents = Seq(classOf[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags])
private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = {
val annotations = mutable.ArrayBuffer[Annotation]()
val suiteHelper = new TestSuiteHelper
suiteHelper.addRocketTestSuites
suiteHelper.addBoomTestSuites
suiteHelper.addArianeTestSuites
// if hwacha parameter exists then generate its tests
// TODO: find a more elegant way to do this. either through
// trying to disambiguate BuildRoCC, having a AccelParamsKey,
// or having the Accelerator/Tile add its own tests
import hwacha.HwachaTestSuites._
if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) {
suiteHelper.addSuites(rv64uv.map(_("p")))
suiteHelper.addSuites(rv64uv.map(_("vp")))
suiteHelper.addSuite(rv64sv("p"))
suiteHelper.addSuite(hwachaBmarks)
annotations += CustomMakefragSnippet(
"SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha")
}
RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations
}
override def transform(annotations: AnnotationSeq): AnnotationSeq = {
val (testSuiteAnnos, oAnnos) = annotations.partition {
case RocketTestSuiteAnnotation(_) => true
case o => false
}
implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance
addTestSuiteAnnotations ++ oAnnos
}
}

49
generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala Normal file
View File

@@ -0,0 +1,49 @@
// See LICENSE for license details.
// Based on Rocket Chip's stage implementation
package chipyard.stage.phases
import scala.collection.mutable
import firrtl.AnnotationSeq
import firrtl.annotations.{Annotation, NoTargetAnnotation}
import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable}
import firrtl.options.Viewer.view
import freechips.rocketchip.stage.RocketChipOptions
import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation}
import freechips.rocketchip.system.TestGeneration
import freechips.rocketchip.util.HasRocketChipStageUtils
trait MakefragSnippet { self: Annotation =>
def toMakefrag: String
}
case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable
/** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */
class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
// Our annotations tend not to be serializable, but are not marked as such.
override val prerequisites = Seq(classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
classOf[chipyard.stage.phases.AddDefaultTests])
override def transform(annotations: AnnotationSeq): AnnotationSeq = {
val targetDir = view[StageOptions](annotations).targetDir
val fileName = s"${view[RocketChipOptions](annotations).longName.get}.d"
val makefragBuilder = new mutable.StringBuilder()
val outputAnnotations = annotations.flatMap {
case RocketTestSuiteAnnotation(tests) =>
// Unfortunately the gen method of TestGeneration is rocketchip package
// private, so we either have to copy code in or use the stateful form
TestGeneration.addSuites(tests)
None
case a: MakefragSnippet =>
makefragBuilder :+ ("\n" + a.toMakefrag)
None
case a => Some(a)
}
writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString)
outputAnnotations
}
}

23
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -8,7 +8,7 @@ import chisel3.experimental.annotate
import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp, HasExtInterruptsModuleImp}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem}
import freechips.rocketchip.tile.{RocketTile}
import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
@@ -56,20 +56,18 @@ class WithBlockDeviceBridge extends OverrideIOBinder({
class WithFASEDBridge extends OverrideIOBinder({
(system: CanHaveMasterAXI4MemPortModuleImp) => {
(system: CanHaveMasterAXI4MemPort with BaseSubsystem) => {
implicit val p = system.p
(system.mem_axi4 zip system.outer.memAXI4Node).flatMap({ case (io, node) =>
(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
axi4Bundle.ar.bits.addr.getWidth,
axi4Bundle.ar.bits.id.getWidth)
FASEDBridge(system.clock, axi4Bundle, system.reset.toBool,
(system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) =>
val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
axi4.ar.bits.addr.getWidth,
axi4.ar.bits.id.getWidth)
FASEDBridge(system.module.clock, axi4, system.module.reset.toBool,
CompleteConfig(p(firesim.configs.MemModelKey),
nastiKey,
Some(AXI4EdgeSummary(edge)),
Some(MainMemoryConsts.globalName)))
})
})
Nil
}
})
@@ -116,9 +114,12 @@ class WithTiedOffSystemGPIO extends OverrideIOBinder({
class WithTiedOffSystemDebug extends OverrideIOBinder({
(system: HasPeripheryDebugModuleImp) => {
Debug.tieoffDebug(system.debug, system.psd)
Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p)
// tieoffDebug doesn't actually tie everything off :/
system.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }))
system.debug.foreach { d =>
d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
d.dmactiveAck := DontCare
}
Nil
}
})

18
generators/firechip/src/main/scala/FireSim.scala
View File

@@ -34,14 +34,24 @@ class FireSim(implicit val p: Parameters) extends RawModule {
val reset = WireInit(false.B)
withClockAndReset(clock, reset) {
// Instantiate multiple instances of the DUT to implement supernode
val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p))
val targets = Seq.fill(p(NumNodes)) {
// It's not a RC bump without some hacks...
// Copy the AsyncClockGroupsKey to generate a fresh node on each
// instantiation of the dut, otherwise the initial instance will be
// reused across each node
import freechips.rocketchip.subsystem.AsyncClockGroupsKey
val lazyModule = p(BuildSystem)(p.alterPartial({
case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy
}))
(lazyModule, Module(lazyModule.module))
}
val peekPokeBridge = PeekPokeBridge(clock, reset)
// A Seq of partial functions that will instantiate the right bridge only
// if that Mixin trait is present in the target's class instance
// if that Mixin trait is present in the target's LazyModule class instance
//
// Apply each partial function to each DUT instance
for ((target) <- targets) {
p(IOBinders).values.map(_(target))
for ((lazyModule, module) <- targets) {
p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module))
NodeIdx.increment()
}
}

13
generators/firechip/src/main/scala/FireSimMulticlockPOC.scala
View File

@@ -64,7 +64,7 @@ class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config
class HalfRateUncore extends WithSingleRationalTileDomain(2,1)
class WithFiresimMulticlockTop extends Config((site, here, up) => {
case BuildSystem => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("system").module)
case BuildSystem => (p: Parameters) => LazyModule(new FiresimMulticlockTop()(p)).suggestName("system")
})
// Complete Config
@@ -88,16 +88,19 @@ class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule {
val reset = WireInit(false.B)
withClockAndReset(refClock, reset) {
// Instantiate multiple instances of the DUT to implement supernode
val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p))
val targets = Seq.fill(p(NumNodes)) {
val lazyModule = p(BuildSystem)(p)
(lazyModule, Module(lazyModule.module))
}
val peekPokeBridge = PeekPokeBridge(refClock, reset)
// A Seq of partial functions that will instantiate the right bridge only
// if that Mixin trait is present in the target's class instance
//
// Apply each partial function to each DUT instance
for ((target) <- targets) {
p(IOBinders).values.map(_(target))
for ((lazyModule, module) <- targets) {
p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module))
}
targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks })
targets.collect({ case (_, t: HasAdditionalClocks) => t.clocks := clockBridge.io.clocks })
}
}

21
generators/firechip/src/main/scala/Generator.scala
View File

@@ -9,7 +9,7 @@ import chisel3.internal.firrtl.{Circuit, Port}
import freechips.rocketchip.diplomacy.{ValName, AutoBundle}
import freechips.rocketchip.devices.debug.DebugIO
import freechips.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts}
import midas.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts}
import freechips.rocketchip.system.DefaultTestSuites._
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
import freechips.rocketchip.config.Parameters
@@ -24,9 +24,11 @@ import chipyard.TestSuiteHelper
trait HasTestSuites {
def addTestSuites(targetName: String, params: Parameters) {
TestSuiteHelper.addRocketTestSuites(params)
TestSuiteHelper.addBoomTestSuites(params)
TestSuiteHelper.addArianeTestSuites(params)
val suiteHelper = new TestSuiteHelper
suiteHelper.addRocketTestSuites(params)
suiteHelper.addBoomTestSuites(params)
suiteHelper.addArianeTestSuites(params)
TestGeneration.addSuites(suiteHelper.suites.values.toSeq)
TestGeneration.addSuite(FastBlockdevTests)
TestGeneration.addSuite(SlowBlockdevTests)
if (!targetName.contains("NoNIC"))
@@ -47,7 +49,7 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu
/** Output software test Makefrags, which provide targets for integration testing. */
def generateTestSuiteMakefrags {
addTestSuites(names.topModuleClass, targetParams)
writeOutputFile(s"$longName.d", TestGeneration.generateMakefrag) // Subsystem-specific test suites
writeOutputFile(s"$longName.d", TestGeneration.generateMakeFrag) // Subsystem-specific test suites
}
// Output miscellaneous files produced as a side-effect of elaboration
@@ -68,12 +70,3 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike {
generateTestSuiteMakefrags
generateArtefacts
}
// For now, provide a separate generator app when not specifically building for FireSim
object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites {
override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
generateFirrtl
generateAnno
generateTestSuiteMakefrags
generateArtefacts
}

2
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -41,7 +41,7 @@ class WithBootROM extends Config((site, here, up) => {
})
class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => {
case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq)
case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq))
})

2
generators/firechip/src/test/scala/ScalaTestSuite.scala
View File

@@ -137,7 +137,7 @@ abstract class FireSimTestSuite(
}
class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config")
class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config")
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") {
runSuite("verilator")(NICLoopbackTests)
}

2
generators/hwacha

Submodule generators/hwacha updated: ef5e5196b6...2706502daf

2
generators/icenet

Submodule generators/icenet updated: b1f957e6eb...4522a3979b

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 4f0cdea85c...9b1907eacb

2
generators/sifive-blocks

Submodule generators/sifive-blocks updated: 1bc0ef18d6...3e35a94d46

2
generators/testchipip

Submodule generators/testchipip updated: d06d7c7dc2...b8d6f21019

1
generators/tracegen/src/main/scala/System.scala
View File

@@ -49,4 +49,3 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
class TraceGenSystemModuleImp(outer: TraceGenSystem)
extends BaseSubsystemModuleImp(outer)
with HasTraceGenTilesModuleImp
with CanHaveMasterAXI4MemPortModuleImp

2
project/build.properties
View File

@@ -1 +1 @@
sbt.version=1.2.8
sbt.version=1.3.2

1
project/plugins.sbt
View File

@@ -14,5 +14,6 @@ addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6")
addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1")
addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3")
addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4")
addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1")
libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1"

2
sims/firesim

Submodule sims/firesim updated: 7c121894e9...f82e115c66

2
tools/barstools

Submodule tools/barstools updated: db6776367c...e230e8cf3f

2
tools/chisel3

Submodule tools/chisel3 updated: d1a6126263...7a343dce95

2
tools/firrtl

Submodule tools/firrtl updated: f738fbe866...eb637777e3

34
variables.mk
View File

@@ -38,43 +38,18 @@ ifeq ($(SUB_PROJECT),chipyard)
TB ?= TestDriver
TOP ?= ChipTop
endif
# for Rocket-chip developers
ifeq ($(SUB_PROJECT),rocketchip)
SBT_PROJECT ?= rocketchip
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
MODEL_PACKAGE ?= freechips.rocketchip.system
CONFIG ?= DefaultConfig
CONFIG_PACKAGE ?= freechips.rocketchip.system
GENERATOR_PACKAGE ?= freechips.rocketchip.system
TB ?= TestDriver
TOP ?= ExampleRocketSystem
endif
# for Hwacha developers
ifeq ($(SUB_PROJECT),hwacha)
SBT_PROJECT ?= hwacha
SBT_PROJECT ?= chipyard
MODEL ?= TestHarness
VLOG_MODEL ?= TestHarness
MODEL_PACKAGE ?= freechips.rocketchip.system
CONFIG ?= HwachaConfig
CONFIG_PACKAGE ?= hwacha
GENERATOR_PACKAGE ?= hwacha
GENERATOR_PACKAGE ?= chipyard
TB ?= TestDriver
TOP ?= ExampleRocketSystem
endif
# Stand-in firechip variables:
# TODO: need a seperate generator and test harnesses for each target
#ifeq ($(SUB_PROJECT),firechip)
# SBT_PROJECT ?= $(SUB_PROJECT)
# MODEL ?= TestHarness
# VLOG_MODEL ?= TestHarness
# MODEL_PACKAGE ?= freechips.rocketchip.system
# CONFIG ?= FireSimRocketChipConfig
# CONFIG_PACKAGE ?= firesim.firesim
# GENERATOR_PACKAGE ?= firesim.firesim
# TB ?= TestDriver
# TOP ?= FireSimNoNIC
#endif
#########################################################################################
# path to rocket-chip and testchipip
@@ -87,11 +62,6 @@ CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl
# names of various files needed to compile and run things
#########################################################################################
long_name = $(MODEL_PACKAGE).$(MODEL).$(CONFIG)
# match the long_name to what the specific generator will output
ifeq ($(GENERATOR_PACKAGE),freechips.rocketchip.system)
long_name=$(CONFIG_PACKAGE).$(CONFIG)
endif
ifeq ($(GENERATOR_PACKAGE),hwacha)
long_name=$(MODEL_PACKAGE).$(CONFIG)
endif